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Massively-parallel bit-serial neural networks for fast epilepsy diagnosis: a feasibility study

Massively-parallel bit-serial neural networks for fast epilepsy diagnosis: a feasibility study
Massively-parallel bit-serial neural networks for fast epilepsy diagnosis: a feasibility study
There are about 1% of the world population suffering from the hidden disability known as epilepsy and major developing countries are not fully equipped to counter this problem. In order to reduce the inconvenience and danger of epilepsy, different methods have been researched by using a artificial neural network (ANN) classification to distinguish epileptic waveforms from normal brain waveforms. This paper outlines the aim of achieving massive ANN parallelization through a dedicated hardware using bit-serial processing. The design of this bit-serial Neural Processing Element (NPE) is presented which implements the functionality of a complete neuron using variable accuracy. The proposed design has been tested taking into consideration non-idealities of a hardware ANN. The NPE consists of a bit-serial multiplier which uses only 16 logic elements on an Altera Cyclone IV FPGA and a bit-serial ALU as well as a look-up table. Arrays of NPEs can be driven by a single controller which executes the neural processing algorithm. In conclusion, the proposed compact NPE design allows the construction of complex hardware ANNs that can be implemented in a portable equipment that suits the needs of a single epileptic patient in his or her daily activities to predict the occurrences of impending tonic conic seizures.
artificial neural networks, bit-serial neural processor, fpga, neural processing element
2010-376X
233 - 237
Kueh, Si Mon
75e25e81-0593-4fc0-9374-93a9cc88235d
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a
Kueh, Si Mon
75e25e81-0593-4fc0-9374-93a9cc88235d
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a

Kueh, Si Mon and Kazmierski, Tom J. (2016) Massively-parallel bit-serial neural networks for fast epilepsy diagnosis: a feasibility study. World Academy of Science, Engineering and Technology, 10 (1), 233 - 237.

Record type: Article

Abstract

There are about 1% of the world population suffering from the hidden disability known as epilepsy and major developing countries are not fully equipped to counter this problem. In order to reduce the inconvenience and danger of epilepsy, different methods have been researched by using a artificial neural network (ANN) classification to distinguish epileptic waveforms from normal brain waveforms. This paper outlines the aim of achieving massive ANN parallelization through a dedicated hardware using bit-serial processing. The design of this bit-serial Neural Processing Element (NPE) is presented which implements the functionality of a complete neuron using variable accuracy. The proposed design has been tested taking into consideration non-idealities of a hardware ANN. The NPE consists of a bit-serial multiplier which uses only 16 logic elements on an Altera Cyclone IV FPGA and a bit-serial ALU as well as a look-up table. Arrays of NPEs can be driven by a single controller which executes the neural processing algorithm. In conclusion, the proposed compact NPE design allows the construction of complex hardware ANNs that can be implemented in a portable equipment that suits the needs of a single epileptic patient in his or her daily activities to predict the occurrences of impending tonic conic seizures.

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Accepted/In Press date: 5 November 2015
Published date: 2016
Keywords: artificial neural networks, bit-serial neural processor, fpga, neural processing element
Organisations: Electronic & Software Systems

Identifiers

Local EPrints ID: 395543
URI: https://eprints.soton.ac.uk/id/eprint/395543
ISSN: 2010-376X
PURE UUID: c8282a13-950a-4490-a44f-39c418479168

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Date deposited: 01 Jun 2016 13:07
Last modified: 05 Oct 2018 12:07

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Contributors

Author: Si Mon Kueh
Author: Tom J. Kazmierski

University divisions

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