Thermal optimization in network-on-chip-based 3D chip multiprocessors using dynamic programming networks
Thermal optimization in network-on-chip-based 3D chip multiprocessors using dynamic programming networks
The substantial silicon density in 3D VLSI, albeit its numerous advantages, introduces serious thermal threats that would lead to faults and system failures. This article introduces a new strategy to effectively diffuse heat from NoC-based 3D CMPs. Runtime Dynamic Programming Network (DPN) is proposed to optimize routing directions and provide silicon temperature moderation. Both on-chip reliability and computational performance have been improved by 63% and 27%, respectively, with the DPN approach. This work enables a new avenue to explore the adaptability for future large-scale 3D integration.
139/1-139/25
Dahir, Nizar
0874e096-12cf-40be-b9eb-2394fca1ebd7
Al-Dujaily, Ra'ed
e7bc6504-5109-478b-a56c-859142c9f77a
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
1 July 2014
Dahir, Nizar
0874e096-12cf-40be-b9eb-2394fca1ebd7
Al-Dujaily, Ra'ed
e7bc6504-5109-478b-a56c-859142c9f77a
Mak, Terrence
0f90ac88-f035-4f92-a62a-7eb92406ea53
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
Dahir, Nizar, Al-Dujaily, Ra'ed, Mak, Terrence and Yakovlev, Alex
(2014)
Thermal optimization in network-on-chip-based 3D chip multiprocessors using dynamic programming networks.
[in special issue: Real-Time and Embedded Technology and Applications, Domain-Specific Multicore Computing, Cross-Layer Dependable Embedded Systems, and Application of Concurrency to System Design (ACSD'13)]
ACM Transactions on Embedded Computing Systems, 13 (4s), , [139].
(doi:10.1145/2584668).
Abstract
The substantial silicon density in 3D VLSI, albeit its numerous advantages, introduces serious thermal threats that would lead to faults and system failures. This article introduces a new strategy to effectively diffuse heat from NoC-based 3D CMPs. Runtime Dynamic Programming Network (DPN) is proposed to optimize routing directions and provide silicon temperature moderation. Both on-chip reliability and computational performance have been improved by 63% and 27%, respectively, with the DPN approach. This work enables a new avenue to explore the adaptability for future large-scale 3D integration.
Text
__soton.ac.uk_UDE_PersonalFiles_Users_skr1c15_mydocuments_eprints_ECS_T Mak_TECS-2012-0168.R1.pdf
- Other
Restricted to Repository staff only
Request a copy
More information
Accepted/In Press date: 4 November 2013
e-pub ahead of print date: 1 July 2014
Published date: 1 July 2014
Organisations:
Electronic & Software Systems
Identifiers
Local EPrints ID: 397439
URI: http://eprints.soton.ac.uk/id/eprint/397439
PURE UUID: 66ccc5de-b7e2-402f-8525-80530fe420fd
Catalogue record
Date deposited: 01 Jul 2016 10:11
Last modified: 15 Mar 2024 01:14
Export record
Altmetrics
Contributors
Author:
Nizar Dahir
Author:
Ra'ed Al-Dujaily
Author:
Terrence Mak
Author:
Alex Yakovlev
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.
View more statistics