This survey considers all ASIC and FPGA implementations of polar decoders that can be found using the Google Scholar search…
“polar decoder” (ASIC, FPGA, VLSI)
It also considers all of their benchmarkers. ASIC results are provided on the first tab, while FPGA results are provided on the second tab.

Results highlighted in yellow have been inferred from the numbers that are provided in the papers, which are shown without highlighting. The method used to infer the value provided in each highlighted cell can be seen in its underlying formula.

Cell AK1 allows the target technology scale to be specified. All throughputs are scaled according to throughput(new)=throughput(old)*scale(old)/scale(new). All latencies are scaled according to latency(new)=latency(old)*scale(new)/scale(old). All areas are scaled according to area(new)=area(old)*scale(new)^2/scale(old)^2. All powers are scaled according to power(new)= power(old)*scale(new)/scale(old).

Note that the area and energy efficiencies are calculated using the encoded throughputs, rather then the data throughputs, since this information is not available for many decoders. The efficiencies are obtained according to areaeff(min) = throughput(encoded,min)/area, areaeff(max) = throughput(encoded,max)/area, energyeff(min) = throughput(encoded,min)/power(max), energyeff(max) = throughput(encoded,max)/power(max). Note that power(max) is used for both energy efficiencies because power(min) is unavailable for most decoders. 

Some decoders support multiple frozen bit sets, although little discussion is provided about how many sets are supported. Some decoders support only a single frozen bit set. For papers that provide no discussion of flexibility, it is assumed that only a single frozen bit set is supported.

This database is made available under the Open Database License: http://opendatacommons.org/licenses/odbl/1.0/. Any rights in individual contents of the database are licensed under the Database Contents License: http://opendatacommons.org/licenses/dbcl/1.0/