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Coarse-grained online monitoring of BTI aging by reusing power gating infrastructure

Coarse-grained online monitoring of BTI aging by reusing power gating infrastructure
Coarse-grained online monitoring of BTI aging by reusing power gating infrastructure
In this paper, we present a novel coarse-grained technique for monitoring online the Bias Temperature Instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during stand-by operations, the value of which depends on the threshold voltage of the CMOS devices in the power-gated design (PGD). It does not require any distributed sensors, because the virtual-power network is already distributed in a PGD. It consists of a hardware block for measuring the discharge time concurrently with normal stand-by operations and a processing block for estimating the BTI aging status of the PGD according to the collected measurements. Through SPICE simulation, we demonstrate that the BTI aging estimation error of the proposed technique is less than 1% and 6.2% for PGDs with static operating frequency and dynamic voltage and frequency scaling, respectively. Its area cost is also found negligible. The power gating Minimum Idle Time (MIT) cost induced by the energy consumed for monitoring the discharge time is evaluated on two scalar machine models using either x86 or ARM instruction sets. It is found less than 1.3X and 1.45X the original power gating MIT, respectively. We validate the proposed technique through accelerated aging experiments conducted with five actual chips that contain an ARM cortex M0 processor, manufactured with a 65nm CMOS technology.
BTI, aging, sensor, power gating, coarse-grained
1063-8210
1397-1407
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Yang, Sheng
04b9848f-ddd4-4d8f-93b6-b91a2144d49c
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Gunn, Steve R.
306af9b3-a7fa-4381-baf9-5d6a6ec89868
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Yang, Sheng
04b9848f-ddd4-4d8f-93b6-b91a2144d49c
Khursheed, Saqib
0c4e3d52-0df5-43d9-bafe-d2eaea457506
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Gunn, Steve R.
306af9b3-a7fa-4381-baf9-5d6a6ec89868

Tenentes, Vasileios, Rossi, Daniele, Yang, Sheng, Khursheed, Saqib, Al-Hashimi, Bashir M. and Gunn, Steve R. (2017) Coarse-grained online monitoring of BTI aging by reusing power gating infrastructure. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25 (4), 1397-1407. (doi:10.1109/TVLSI.2016.2626218).

Record type: Article

Abstract

In this paper, we present a novel coarse-grained technique for monitoring online the Bias Temperature Instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during stand-by operations, the value of which depends on the threshold voltage of the CMOS devices in the power-gated design (PGD). It does not require any distributed sensors, because the virtual-power network is already distributed in a PGD. It consists of a hardware block for measuring the discharge time concurrently with normal stand-by operations and a processing block for estimating the BTI aging status of the PGD according to the collected measurements. Through SPICE simulation, we demonstrate that the BTI aging estimation error of the proposed technique is less than 1% and 6.2% for PGDs with static operating frequency and dynamic voltage and frequency scaling, respectively. Its area cost is also found negligible. The power gating Minimum Idle Time (MIT) cost induced by the energy consumed for monitoring the discharge time is evaluated on two scalar machine models using either x86 or ARM instruction sets. It is found less than 1.3X and 1.45X the original power gating MIT, respectively. We validate the proposed technique through accelerated aging experiments conducted with five actual chips that contain an ARM cortex M0 processor, manufactured with a 65nm CMOS technology.

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More information

Accepted/In Press date: 30 October 2016
e-pub ahead of print date: 2 December 2016
Published date: April 2017
Additional Information: © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Keywords: BTI, aging, sensor, power gating, coarse-grained
Organisations: Electronics & Computer Science

Identifiers

Local EPrints ID: 402282
URI: https://eprints.soton.ac.uk/id/eprint/402282
ISSN: 1063-8210
PURE UUID: 2bbd176f-3d67-43a3-bd1f-4e87f313c807

Catalogue record

Date deposited: 11 Nov 2016 11:17
Last modified: 02 Dec 2019 19:51

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