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A high-throughput FPGA architecture for joint source and channel decoding

A high-throughput FPGA architecture for joint source and channel decoding
A high-throughput FPGA architecture for joint source and channel decoding
2921-2944
Brejza, Matthew
a761342e-e140-45a7-ad48-095a6628af17
Maunder, Rob
76099323-7d58-4732-a98f-22a662ccba6c
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Hanzo, Lajos
66e7266f-3066-4fc0-8391-e000acce71a1
Brejza, Matthew
a761342e-e140-45a7-ad48-095a6628af17
Maunder, Rob
76099323-7d58-4732-a98f-22a662ccba6c
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Hanzo, Lajos
66e7266f-3066-4fc0-8391-e000acce71a1

Brejza, Matthew, Maunder, Rob, Al-Hashimi, Bashir and Hanzo, Lajos (2016) A high-throughput FPGA architecture for joint source and channel decoding. IEEE Access, 5, 2921-2944. (doi:10.1109/ACCESS.2016.2633441).

Record type: Article
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Accepted/In Press date: 19 November 2016
Published date: 29 November 2016
Organisations: Southampton Wireless Group
Learn more about Southampton Wireless Group research

Identifiers

Local EPrints ID: 403328
URI: http://eprints.soton.ac.uk/id/eprint/403328
DOI: doi:10.1109/ACCESS.2016.2633441
PURE UUID: 0a705435-0e56-4b05-ac1c-fd34ce0f6058
ORCID for Rob Maunder: ORCID iD orcid.org/0000-0002-7944-2615
ORCID for Lajos Hanzo: ORCID iD orcid.org/0000-0002-2636-5214

Catalogue record

Date deposited: 25 Nov 2016 21:55
Last modified: 18 Mar 2024 03:09

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Contributors

Author: Matthew Brejza
Author: Rob Maunder ORCID iD
Author: Bashir Al-Hashimi
Author: Lajos Hanzo ORCID iD

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