A data-driven Verilog-A ReRam model
A data-driven Verilog-A ReRam model
The translation of emerging application concepts that exploit Resistive Random Access Memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model where device current-voltage characteristics and resistive switching rate are expressed as a function of a) bias voltage and b) initial resistive state. The model’s versatility is validated on detailed characterization data, for both filamentary valence change memory and non-filamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing resistive state response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.
1-12
Messaris, Ioannis
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Serb, Alexander
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Khiat, Ali
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Nikolaidis, Spyridon
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Prodromakis, Themis
d58c9c10-9d25-4d22-b155-06c8437acfbf
Messaris, Ioannis
312befd2-f699-4e85-9c52-6715aaa757d7
Serb, Alexander
30f5ec26-f51d-42b3-85fd-0325a27a792c
Khiat, Ali
bf549ddd-5356-4a7d-9c12-eb6c0d904050
Nikolaidis, Spyridon
4c90a3e0-0ca7-447c-be50-d2de2578e3f7
Prodromakis, Themis
d58c9c10-9d25-4d22-b155-06c8437acfbf
Messaris, Ioannis, Serb, Alexander, Khiat, Ali, Nikolaidis, Spyridon and Prodromakis, Themis
(2018)
A data-driven Verilog-A ReRam model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, .
(doi:10.1109/TCAD.2018.2791468).
Abstract
The translation of emerging application concepts that exploit Resistive Random Access Memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model where device current-voltage characteristics and resistive switching rate are expressed as a function of a) bias voltage and b) initial resistive state. The model’s versatility is validated on detailed characterization data, for both filamentary valence change memory and non-filamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing resistive state response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.
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- Author's Original
Text
A Data Driven Verilog-A ReRAM Model
- Accepted Manuscript
More information
Submitted date: 2016
Accepted/In Press date: 20 December 2017
e-pub ahead of print date: 9 January 2018
Additional Information:
This work has been submitted to the IEEE for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessible
Organisations:
Nanoelectronics and Nanotechnology
Identifiers
Local EPrints ID: 403644
URI: http://eprints.soton.ac.uk/id/eprint/403644
ISSN: 0278-0070
PURE UUID: 1a5ddca3-e96b-42c3-b003-ebf427fee4a5
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Date deposited: 07 Dec 2016 13:07
Last modified: 15 Mar 2024 03:47
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Contributors
Author:
Ioannis Messaris
Author:
Alexander Serb
Author:
Ali Khiat
Author:
Spyridon Nikolaidis
Author:
Themis Prodromakis
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