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A compact low-noise broadband digital picoammeter architecture

A compact low-noise broadband digital picoammeter architecture
A compact low-noise broadband digital picoammeter architecture
A low-noise (?4 fA/?Hz), broadband (?100 kHz) compact architecture and related operation solutions are proposed for portable and low-cost time-domain acquisition of currents with effective resolution in the order of 1 pA and below. The front-end architecture is based on an integrating-differentiating scheme to achieve the optimal performance in terms of input-referred equivalent noise, but it overcomes the typical noise/bandwidth trade-off by making the sampling frequency of the A/D conversion independent from the rate at which the analog front-end is reset. In order to strongly mitigate the main drawback, i.e., the introduction in the system of an inherent time-variance, a Track-and-Hold circuit synchronized with the reset is exploited.

For validation purposes, a dual-channel prototype was implemented in a low-cost CMOS technology. The prototype is characterized by standard figures of merit and is experimentally validated by two simple case studies, which are typical of practical applications.
194-204
Crescentini, M.
a9930dc7-21a4-4582-9c17-a40b2b6eb7e3
Tartagni, M.
dfdda9ee-a432-4a57-bde4-e538b963600f
Morgan, H.
de00d59f-a5a2-48c4-a99a-1d5dd7854174
Traverso, P.A.
7af4c024-d8f4-4cc8-bd5a-7322af943613
Crescentini, M.
a9930dc7-21a4-4582-9c17-a40b2b6eb7e3
Tartagni, M.
dfdda9ee-a432-4a57-bde4-e538b963600f
Morgan, H.
de00d59f-a5a2-48c4-a99a-1d5dd7854174
Traverso, P.A.
7af4c024-d8f4-4cc8-bd5a-7322af943613

Crescentini, M., Tartagni, M., Morgan, H. and Traverso, P.A. (2017) A compact low-noise broadband digital picoammeter architecture. Measurement, 100, 194-204. (doi:10.1016/j.measurement.2016.12.040).

Record type: Article

Abstract

A low-noise (?4 fA/?Hz), broadband (?100 kHz) compact architecture and related operation solutions are proposed for portable and low-cost time-domain acquisition of currents with effective resolution in the order of 1 pA and below. The front-end architecture is based on an integrating-differentiating scheme to achieve the optimal performance in terms of input-referred equivalent noise, but it overcomes the typical noise/bandwidth trade-off by making the sampling frequency of the A/D conversion independent from the rate at which the analog front-end is reset. In order to strongly mitigate the main drawback, i.e., the introduction in the system of an inherent time-variance, a Track-and-Hold circuit synchronized with the reset is exploited.

For validation purposes, a dual-channel prototype was implemented in a low-cost CMOS technology. The prototype is characterized by standard figures of merit and is experimentally validated by two simple case studies, which are typical of practical applications.

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Accepted/In Press date: 25 December 2016
e-pub ahead of print date: 28 December 2016
Published date: March 2017
Organisations: Nanoelectronics and Nanotechnology

Identifiers

Local EPrints ID: 404933
URI: https://eprints.soton.ac.uk/id/eprint/404933
PURE UUID: 3d43f3a8-bab5-4637-8eb2-9ca782700f5c
ORCID for H. Morgan: ORCID iD orcid.org/0000-0003-4850-5676

Catalogue record

Date deposited: 25 Jan 2017 09:57
Last modified: 17 Sep 2019 05:05

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