****** Logic Analyser Experiment Results ******
 **************** 27/03/2015 ****************

These results measure the performance of the time synchronisation method,
running on 9 eZ430-RF2500 sensor nodes in a 3x3 grid.  The data is captured from
2 Saleae logic analysers running in parallel - this was done because
each analyser only has 1 channel and I couldn't get a logic analyser with
more channels to do what I needed!

The results record what's going on in each sensor node over time.  A GPIO
pin (pin 12) was used on each node to output the time sync state.  The
rising and falling edges tell us when the node is on, and also when each
new frame begins.

The trace for one node over a single frame might look something like the following:
                  .------------.    .------------.
------------------'            '----'            '-------------------------
The results capture ~100 frames (over about 400 seconds).

The first rising edge shows when the node is turned on.  Whenever a '1' is
asserted the node is in Rx mode.  Due to the limited channels available we have
to use the same channel to show when the timer reaches 0 (start of Tx window) -
this happens at the first falling edge.  The node asserts '1' again once the node
finishes its Tx and the final falling edge shows when the node turns off.

In terms of synchronisation the most important part of the waveform is the time of 
the first falling edge - the start of the Tx window.  The most important thing
is that all nodes share a common 0 timer value.

*****

The results are taken from 2 logic analysers run in parallel.  Both started
capturing data at roughly the same time, but the two results need to be
precisely aligned.  This was done by sharing a common channel between both
analysers.  The offset can then be calculated and as timestamps are measured
in seconds, it is possible to align the two data sets.  The separate data
from both analysers is combined in a single file, in which the nodes have
also been rearranged to be in ascending order.