Using Iddt current degradation to monitor ageing in CMOS circuits

Bin Ramlee, Radi Husin and Zwolinski, Mark (2016) Using Iddt current degradation to monitor ageing in CMOS circuits. International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016), Bremen, Germany. 20 - 22 Sep 2016. pp. 200-204 . (doi:10.1109/PATMOS.2016.7833688).

Record type: Conference or Workshop Item (Paper)

Abstract

This paper presents an alternative means for measuring the Iddt current degradation with circuit ageing. MOS devices for CMOS process technologies below 45nm are known to be susceptible to ageing effects such as BTI and HCI. The correlation between the supply current degradation and the propagation delay degradation is shown to provide crucial information in monitoring circuit ageing. Ageing analysis were conducted for various CMOS circuits and the ALU of OpenRisc 1200 processor using 32nm process technology. Results showed that the Iddt current degradation may vary up to -11.97% compared to delay degradation of 7.15% of the same critical path. A significant Iddt current degradation of -23.34% can be observed for the ALU circuit block. Evaluating the Iddt current degradation in a wider perspective provides not only a better percentage change, it also provides a much bigger absolute current.

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Published date: 21 September 2016

Venue - Dates: International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016), Bremen, Germany, 2016-09-20 - 2016-09-22

Organisations: Electronics & Computer Science, EEE

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