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Energy efficient bootstrapped CMOS inverter for ultra-low power applications

Energy efficient bootstrapped CMOS inverter for ultra-low power applications
Energy efficient bootstrapped CMOS inverter for ultra-low power applications
This paper describes an energy efficient boot-strapped CMOS inverter for ultra-low power applications. The proposed design is achieved by internally boosting the gate voltage of the transistors (via the charge pumping technique), and the operating region is shifted from the sub-threshold to a higher region, enhancing performance and improving tolerance to PVT variations. Despite the proposed bootstrapped driver operates with a sub-threshold power supply it uses fewer transistors engaging in this region by utilizing two stages. The first stage is a normal driver with PMOS and NMOS transistors that are driven by the enhancing voltage circuit (stage 2) which generates voltage levels theoretically between -VDD for pulling up to 2Vdd for pulling down. Our analysis shows that the proposed implementation achieves around 20% reduction in energy consumption compared to conventional designs under a supply voltage of 0.15V VDD.
516-519
IEEE
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
AL-Dallo, Mohammed
b3859744-82a8-43d3-a3fb-db3cec08068a
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
AL-Dallo, Mohammed
b3859744-82a8-43d3-a3fb-db3cec08068a
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33

Yakovlev, Alex, AL-Dallo, Mohammed and Halak, Basel (2017) Energy efficient bootstrapped CMOS inverter for ultra-low power applications. In 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS),. IEEE. pp. 516-519 . (doi:10.1109/ICECS.2016.7841252).

Record type: Conference or Workshop Item (Paper)

Abstract

This paper describes an energy efficient boot-strapped CMOS inverter for ultra-low power applications. The proposed design is achieved by internally boosting the gate voltage of the transistors (via the charge pumping technique), and the operating region is shifted from the sub-threshold to a higher region, enhancing performance and improving tolerance to PVT variations. Despite the proposed bootstrapped driver operates with a sub-threshold power supply it uses fewer transistors engaging in this region by utilizing two stages. The first stage is a normal driver with PMOS and NMOS transistors that are driven by the enhancing voltage circuit (stage 2) which generates voltage levels theoretically between -VDD for pulling up to 2Vdd for pulling down. Our analysis shows that the proposed implementation achieves around 20% reduction in energy consumption compared to conventional designs under a supply voltage of 0.15V VDD.

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More information

Accepted/In Press date: 1 February 2017
Published date: 6 February 2017
Organisations: EEE

Identifiers

Local EPrints ID: 407838
URI: http://eprints.soton.ac.uk/id/eprint/407838
PURE UUID: cb08acba-814b-442f-80a9-973b4b2f8945
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226

Catalogue record

Date deposited: 27 Apr 2017 01:01
Last modified: 16 Mar 2024 04:07

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Contributors

Author: Alex Yakovlev
Author: Mohammed AL-Dallo
Author: Basel Halak ORCID iD

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