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Course on secure hardware design of silicon chips

Halak, Basel (2017) Course on secure hardware design of silicon chips IET Circuits, Devices & Systems, 11, (4), pp. 304-309. (doi:10.1049/iet-cds.2017.0028).

Record type: Article

Abstract

This study describes the design and evaluation of a secure chip design module for graduate students and junior engineers with electronics and computer engineering. This course has two broad goals, the first is to teach students how design complex systems on chips using industry standard tools and the second is to educate them on emerging hardware security threats and countermeasures. There are a number of strategies currently been employed to handle the rising complexity of chip design, namely reuse, abstraction and automation. The authors aim to show how to employ these approaches to produce working systems within a time-constrained environment similar to that of IC design companies. One of the unique features of this module is its approach of treating hardware security as an integral part of the chip design process and as one of the design metrics which can be evaluated and optimised, this allows students to better understand the root causes of this issue and to think more constructively about potential countermeasures. The course is designed based on the principles of constructive alignment method and Kolb learning cycle. Detailed syllabus and assessment exercises are included. Feedback results from students' surveys indicate that the module has been positively received.

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More information

Accepted/In Press date: 24 February 2017
e-pub ahead of print date: 18 April 2017
Published date: 4 September 2017
Organisations: EEE

Identifiers

Local EPrints ID: 407858
URI: http://eprints.soton.ac.uk/id/eprint/407858
ISSN: 1751-858X
PURE UUID: 364ae8f8-47b1-44a0-8aa1-7a1ea8b693a7

Catalogue record

Date deposited: 27 Apr 2017 01:07
Last modified: 18 Sep 2017 16:32

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Contributors

Author: Basel Halak

University divisions

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