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Low power probabilistic online monitoring of systematic erroneous behaviour

Low power probabilistic online monitoring of systematic erroneous behaviour
Low power probabilistic online monitoring of systematic erroneous behaviour
Electronic devices with power-constrained embedded systems are used for a variety of IoT applications, such as geo-monitoring, parking sensors and surveillance, which may tolerate few errors and may not be constrained by a strict error detection latency requirement. In this poster, we propose a novel low power online error monitoring technique that produces an alarm signal when systematic erroneous behaviour has occurred over a pre-defined time interval. A monitoring architecture monitors the signal probabilities of the logic cones concurrently to its normal operation and compares them on-chip against the signature of error-free behaviour. Results on a set of the EPFL’15 benchmarks show an average error coverage of 82.9%% of errors induced by stuck-at faults, with an average area cost of 1.2% and an error detection latency of [0.01, 3.3] milliseconds.
IEEE
Gutierrez Alcala, Mauricio, D.
29838e60-f993-48e7-8133-0d0ff32129fa
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Kazmierski, Tomasz J.
a97d7958-40c3-413f-924d-84545216092a
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Gutierrez Alcala, Mauricio, D.
29838e60-f993-48e7-8133-0d0ff32129fa
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Kazmierski, Tomasz J.
a97d7958-40c3-413f-924d-84545216092a
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f

Gutierrez Alcala, Mauricio, D., Tenentes, Vasileios, Kazmierski, Tomasz J. and Rossi, Daniele (2017) Low power probabilistic online monitoring of systematic erroneous behaviour. In 2017 22d IEEE Test Symposium (ETS). IEEE. 2 pp . (doi:10.1109/ETS.2017.7968239).

Record type: Conference or Workshop Item (Paper)

Abstract

Electronic devices with power-constrained embedded systems are used for a variety of IoT applications, such as geo-monitoring, parking sensors and surveillance, which may tolerate few errors and may not be constrained by a strict error detection latency requirement. In this poster, we propose a novel low power online error monitoring technique that produces an alarm signal when systematic erroneous behaviour has occurred over a pre-defined time interval. A monitoring architecture monitors the signal probabilities of the logic cones concurrently to its normal operation and compares them on-chip against the signature of error-free behaviour. Results on a set of the EPFL’15 benchmarks show an average error coverage of 82.9%% of errors induced by stuck-at faults, with an average area cost of 1.2% and an error detection latency of [0.01, 3.3] milliseconds.

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Accepted/In Press date: 10 February 2017
e-pub ahead of print date: 7 July 2017
Published date: July 2017
Venue - Dates: IEEE European Test Symposium, Limassol, Cyprus, 2017-05-22 - 2017-05-26
Organisations: Electronics & Computer Science, Electronic & Software Systems

Identifiers

Local EPrints ID: 408393
URI: https://eprints.soton.ac.uk/id/eprint/408393
PURE UUID: 13f6266e-42ec-4c89-ba81-ed7442f3d33e

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Date deposited: 19 May 2017 04:05
Last modified: 02 Dec 2019 18:52

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Contributors

Author: Mauricio, D. Gutierrez Alcala
Author: Vasileios Tenentes
Author: Tomasz J. Kazmierski
Author: Daniele Rossi

University divisions

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