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Susceptible workload evaluation and protection using selective fault tolerance

Susceptible workload evaluation and protection using selective fault tolerance
Susceptible workload evaluation and protection using selective fault tolerance
Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in the presence of faults not all workloads are equally susceptible to errors. In this paper, we present a low power fault tolerance design technique that selects and protects the most susceptible workload. We propose to rank the workload susceptibility as the likelihood of any error to bypass the logic masking of the circuit and propagate to its outputs. The susceptible workload is protected by a partial Triple Modular Redundancy (TMR) scheme. We evaluate the proposed technique on timing-independent and timing-dependent errors induced by permanent and transient faults. In comparison with unranked selective fault tolerance approach, we demonstrate a) a similar error coverage with a 39.7% average reduction of the area overhead or b) a 86.9% average error coverage improvement for a similar area overhead. For the same area overhead case, we observe an error coverage improvement of 53.1% and 53.5% against permanent stuck-at and transition faults, respectively, and an average error coverage improvement of 151.8% and 89.0% against timing-dependent and timing-independent transient faults, respectively. Compared to TMR, the proposed technique achieves an area and power overhead reduction of 145.8% to 182.0%.
Selective fault tolerance, Workload susceptibility analysis, Susceptible workload, Output deviations, Permanent faults, Transient Faults
0923-8174
463–477
Gutierrez Alcala, Mauricio, Daniel
29838e60-f993-48e7-8133-0d0ff32129fa
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Kazmierski, Tomasz
a97d7958-40c3-413f-924d-84545216092a
Gutierrez Alcala, Mauricio, Daniel
29838e60-f993-48e7-8133-0d0ff32129fa
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Kazmierski, Tomasz
a97d7958-40c3-413f-924d-84545216092a

Gutierrez Alcala, Mauricio, Daniel, Tenentes, Vasileios, Rossi, Daniele and Kazmierski, Tomasz (2017) Susceptible workload evaluation and protection using selective fault tolerance. Journal of Electronic Testing, 33 (4), 463–477. (doi:10.1007/s10836-017-5668-7).

Record type: Article

Abstract

Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in the presence of faults not all workloads are equally susceptible to errors. In this paper, we present a low power fault tolerance design technique that selects and protects the most susceptible workload. We propose to rank the workload susceptibility as the likelihood of any error to bypass the logic masking of the circuit and propagate to its outputs. The susceptible workload is protected by a partial Triple Modular Redundancy (TMR) scheme. We evaluate the proposed technique on timing-independent and timing-dependent errors induced by permanent and transient faults. In comparison with unranked selective fault tolerance approach, we demonstrate a) a similar error coverage with a 39.7% average reduction of the area overhead or b) a 86.9% average error coverage improvement for a similar area overhead. For the same area overhead case, we observe an error coverage improvement of 53.1% and 53.5% against permanent stuck-at and transition faults, respectively, and an average error coverage improvement of 151.8% and 89.0% against timing-dependent and timing-independent transient faults, respectively. Compared to TMR, the proposed technique achieves an area and power overhead reduction of 145.8% to 182.0%.

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Accepted/In Press date: 5 June 2017
e-pub ahead of print date: 20 June 2017
Published date: August 2017
Keywords: Selective fault tolerance, Workload susceptibility analysis, Susceptible workload, Output deviations, Permanent faults, Transient Faults
Organisations: Electronics & Computer Science, Electronic & Software Systems

Identifiers

Local EPrints ID: 411912
URI: https://eprints.soton.ac.uk/id/eprint/411912
ISSN: 0923-8174
PURE UUID: b54f9e12-5c71-40a8-b00a-ccdf133dcfb4

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Date deposited: 29 Jun 2017 16:31
Last modified: 25 Nov 2019 18:55

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Contributors

Author: Mauricio, Daniel Gutierrez Alcala
Author: Vasileios Tenentes
Author: Daniele Rossi
Author: Tomasz Kazmierski

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