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Evaluation and analysis of single-phase clock flip-flops for NTV applications

Evaluation and analysis of single-phase clock flip-flops for NTV applications
Evaluation and analysis of single-phase clock flip-flops for NTV applications
Performance slack in IoT applications is routinely exploited in sensor nodes to minimize power by aggressive voltage scaling. However, scaling voltage to sub-threshold levels causes severe degradation in performance and is prone to On Chip Variation (OCV). In contrast, Near Threshold Voltage (NTV) operation offers a good balance between performance loss, OCV and energy reduction and is promising for industry adoption. Unlike sub-threshold operation, where leakage power dominates, NTV designs benefit from dynamic power saving techniques, such as Single-Phase Clocked Flip-Flops (SPC FFs), which eliminate internal clock buffers. In this context, this work reviews prominent types of state-of-the-art SPC FFs and analyses their suitability for NTV operation. Five SPC FFs are reviewed and based on a preliminary analysis, two designs, which meet all NTV circuit design requirements are further investigated. These SPC FFs are designed for NTV operation in TSMC 65LP and compared against the classic transmission gate FF (TGFF). Celllevel design issues and variation are explored in the context of a 5000 gate AES encryption macro. Key design issues are identified, which erode the claimed benefits of SPC FFs when implemented as part of a larger design. We conclude that aggressive reduction in FF clock loading offers benefits but can lead to functional failures when OCV is considered, especially at NTV. Given the theoretical benefits of SPC FFs for enabling IoT, the need for further work on SPC FF designs is highlighted.
IEEE
Cai, Yunpeng
dbb0299d-11fa-416f-8785-095704dea862
Savanth, Parameshwarappa Anand, Kumar
57b60ac8-bbb6-4517-9d5e-668d82500190
Prabhat, Pranay
6d246b81-a756-431c-865c-2f58e0d03008
Myers, James
b541d1fd-a24a-4771-91b3-84e1ac8c7fe5
Weddell, Alexander
3d8c4d63-19b1-4072-a779-84d487fd6f03
Kazmierski, Tomasz
a97d7958-40c3-413f-924d-84545216092a
Cai, Yunpeng
dbb0299d-11fa-416f-8785-095704dea862
Savanth, Parameshwarappa Anand, Kumar
57b60ac8-bbb6-4517-9d5e-668d82500190
Prabhat, Pranay
6d246b81-a756-431c-865c-2f58e0d03008
Myers, James
b541d1fd-a24a-4771-91b3-84e1ac8c7fe5
Weddell, Alexander
3d8c4d63-19b1-4072-a779-84d487fd6f03
Kazmierski, Tomasz
a97d7958-40c3-413f-924d-84545216092a

Cai, Yunpeng, Savanth, Parameshwarappa Anand, Kumar, Prabhat, Pranay, Myers, James, Weddell, Alexander and Kazmierski, Tomasz (2017) Evaluation and analysis of single-phase clock flip-flops for NTV applications. In 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE. 6 pp. (doi:10.1109/PATMOS.2017.8106962).

Record type: Conference or Workshop Item (Paper)

Abstract

Performance slack in IoT applications is routinely exploited in sensor nodes to minimize power by aggressive voltage scaling. However, scaling voltage to sub-threshold levels causes severe degradation in performance and is prone to On Chip Variation (OCV). In contrast, Near Threshold Voltage (NTV) operation offers a good balance between performance loss, OCV and energy reduction and is promising for industry adoption. Unlike sub-threshold operation, where leakage power dominates, NTV designs benefit from dynamic power saving techniques, such as Single-Phase Clocked Flip-Flops (SPC FFs), which eliminate internal clock buffers. In this context, this work reviews prominent types of state-of-the-art SPC FFs and analyses their suitability for NTV operation. Five SPC FFs are reviewed and based on a preliminary analysis, two designs, which meet all NTV circuit design requirements are further investigated. These SPC FFs are designed for NTV operation in TSMC 65LP and compared against the classic transmission gate FF (TGFF). Celllevel design issues and variation are explored in the context of a 5000 gate AES encryption macro. Key design issues are identified, which erode the claimed benefits of SPC FFs when implemented as part of a larger design. We conclude that aggressive reduction in FF clock loading offers benefits but can lead to functional failures when OCV is considered, especially at NTV. Given the theoretical benefits of SPC FFs for enabling IoT, the need for further work on SPC FF designs is highlighted.

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Published date: September 2017
Venue - Dates: 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, Thessaloniki, Greece, 2017-07-25 - 2017-07-27

Identifiers

Local EPrints ID: 412273
URI: https://eprints.soton.ac.uk/id/eprint/412273
PURE UUID: f05cc3c6-c36e-45a6-8d65-75503abf25ad
ORCID for Alexander Weddell: ORCID iD orcid.org/0000-0002-6763-5460

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Date deposited: 24 Aug 2017 16:30
Last modified: 14 Jun 2018 00:33

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Contributors

Author: Yunpeng Cai
Author: Parameshwarappa Anand, Kumar Savanth
Author: Pranay Prabhat
Author: James Myers
Author: Alexander Weddell ORCID iD
Author: Tomasz Kazmierski

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