This dataset supports the article entitled "Empirical CPU Power Modelling and Estimation in the gem5 Simulator" accepted for publication in 27th International Symposium on Power and Timing Modeling, Optimization and Simulation, September 2017.

Data Supporting Figures:

Fig. 3 - Difference between the hardware platform and gem5 model in terms PMCs/activity statistics and execution time (Frequency=1 GHz). Equivalent
performance events shown in Table II

Fig. 4 - Mean Absolute Percentage Error (MAPE) for each workload, aggregated over every DVFS level and core mapping.

Fig. 5 - Breakdown of modelled power into smaller components. The static power components includes background switching activity.

Fig. 6 - Modelled power for each workload @1000 MHz.

Fig. 7 - Difference in power between hardware model and gem5 model at different frequencies (MHz).