Dataset for paper "Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs"

The tabs in the spreadsheet contain the data for the figures and the tables of the paper. Therefore, the tabs are labeled according to figure/tables.

Fig 3: Leakage current at stand-by Isb obtained by DC analysis and sweeping
a resistive bridge R between Vdd and VVdd in the range R \in [10
Ohm; 1GOhm
]

TABLE I: THE BENCHMARK CIRCUITS AND THEIR RELATIVE POWER CONSUMPTION FOR FAULT-FREE AND FAULTY CASES THAT DO NOT AFFECT FUNCTIONALITY

Fig. 4: DC analysis results ofVV dd at stand-by when we sweep a bridge defect between Vdd and VVdd; and leakage current Isb is affected
exponentially by VVdd@sb

Fig. 6: Fitted models of the Isb for benchmarks using eq (2) and SPICE measurements with correlation coefficient values greater than 99.9%

Fig. 8: characteristics functions of VCOs after calibration

Fig. 9: AC analysis of bridges at power rails and stuck-on power switches

Fig. 11: Estimated voltage and sampling error for sampling times s = 0:5; 1 and 2 ns for N-Counter and P-Counter

Fig. 12. Expected diagnosis error ERx when VVdd@sb < Vdd/2; and VVdd@sb > Vdd/2

TABLE II: SAMPLING BLOCK SETUP, SENSOR SAMPLING VOLTAGE ERROR (EVx) AND PROPOSED AREA OVERHEAD FOR A SET OF IWLS CIRCUITS

Fig. 13. Trade-off between the absolute sampling voltage errors |EVx| and the size of P-Counter and N-Counter |X|

Fig. 14. Expected (ERx) and actual (‘x’ points) diagnosis error for random bridges as a function of the measured virtual voltage (Vx) for sampling setups
exhibiting a sampling error of (a)(b) 8mV; (c)(d)4mV; and (e)(f) 2mV; and bridges with (a)(c)(d) VVdd@sb<Vdd/2; and VVdd@sb > Vdd/2

TABLE III: POWER ESTIMATION ERROR (EIx), DIAGNOSIS ERROR (ERx), ACCURACY (ACC.), AND RESOLUTION (DRx) ON A SET OF CIRCUITS

Fig. 15. Monte Carlo simulations for exploring the VV dd@sb variability induced by process variation for r = 10%, 20%