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An ageing-aware Digital Synthesis Approach

Duan, Shengyu, Halak, Basel and Zwolinski, Mark (2017) An ageing-aware Digital Synthesis Approach In 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design: SMACD 2017. IEEE..

Record type: Conference or Workshop Item (Paper)


Due to the shrinkage of CMOS technology, wear-out
mechanisms such as Bias Temperature Instability (BTI) have
raised growing concerns for circuit reliability. BTI can cause
a threshold voltage shift in CMOS devices and consequently
increase circuit delay. This paper presents an ageing-aware gate-level
optimization approach that can be used in a modern
synthesis process. It aims to optimize a circuit to give improved
lifetime reliability under given area and timing constraints. A new
sensitivity metric is proposed as a function of area increase, delay
reduction, degradation reduction and design constraints. This
sensitivity metric can be adjusted to select the most favourable
gates in terms of circuit timing, lifetime or both. By iteratively
up-sizing the gates with the highest sensitivity, our proposed
optimization flow can meet any realizable area and timing
constraints, to give up to 3.3x lifetime improvement.

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Published date: 12 June 2017


Local EPrints ID: 412726
PURE UUID: 2a413fc0-a6b7-4167-9836-72139450af12
ORCID for Mark Zwolinski: ORCID iD

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Date deposited: 27 Jul 2017 16:30
Last modified: 27 Jul 2017 16:30

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Author: Shengyu Duan
Author: Basel Halak
Author: Mark Zwolinski ORCID iD

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