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Exploiting aging benefits for the design of reliable drowsy cache memories

Exploiting aging benefits for the design of reliable drowsy cache memories
Exploiting aging benefits for the design of reliable drowsy cache memories
In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling (DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI) in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in sub-threshold current due to BTI aging. We develop a simulation framework to evaluate trade-offs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead.
0278-0070
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Reddy, Sudhakar
67e0e9b9-8788-489d-a0ed-7e42ab85594b
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Brown, Andrew
5c19e523-65ec-499b-9e7c-91522017d7e0
Rossi, Daniele
30c42382-cf0a-447d-8695-fa229b7b8a2f
Tenentes, Vasileios
1bff9ebc-9186-438b-850e-6c738994fa39
Reddy, Sudhakar
67e0e9b9-8788-489d-a0ed-7e42ab85594b
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Brown, Andrew
5c19e523-65ec-499b-9e7c-91522017d7e0

Rossi, Daniele, Tenentes, Vasileios, Reddy, Sudhakar, Al-Hashimi, Bashir and Brown, Andrew (2017) Exploiting aging benefits for the design of reliable drowsy cache memories. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (doi:10.1109/TCAD.2017.2729399).

Record type: Article

Abstract

In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling (DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI) in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in sub-threshold current due to BTI aging. We develop a simulation framework to evaluate trade-offs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead.

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Accepted/In Press date: 31 May 2017
e-pub ahead of print date: 19 July 2017

Identifiers

Local EPrints ID: 412770
URI: https://eprints.soton.ac.uk/id/eprint/412770
ISSN: 0278-0070
PURE UUID: d445ecf1-e723-4b9e-9d97-aba825a6eaa2

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Date deposited: 01 Aug 2017 16:31
Last modified: 09 Dec 2019 18:43

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Contributors

Author: Daniele Rossi
Author: Vasileios Tenentes
Author: Sudhakar Reddy
Author: Bashir Al-Hashimi
Author: Andrew Brown

University divisions

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