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CPU power estimation using PMCs and its application in gem5

CPU power estimation using PMCs and its application in gem5
CPU power estimation using PMCs and its application in gem5
Fast and accurate estimation of CPU power consumption is necessary to inform run-time power management approaches and allow effective design space exploration. Power simulators, combined with a full-system architectural simulator such as gem5, enable power-performance trade-offs to be investigated early in the design of a system. However, the accuracy of existing power simulators is known to be low, and this can lead to incorrect conclusions being made. In this talk, I will present our statistically rigorous methodology for building accurate run-time power models using Performance Monitoring Counters (PMCs) for mobile and embedded devices, and demonstrate how our models make more efficient use of limited training data and better adapt to unseen scenarios by uniquely considering stability. Models built using the methodology for both ARM Cortex-A7 and Cortex-A15 CPUs exhibit a 3.8% and 2.8% average error respectively. I will also present online resources that we have made available from the work, including software tools, documentation, raw data and further results. I will also present results from an investigation into the correlation between gem5 activity statistics and hardware PMCs. Based on this, a gem5 power model for a simulated quadcore ARM Cortex-A15 has been created, built using the above methodology, and its accuracy compared against experimental results obtained from hardware.
Merrett, Geoffrey
89b3a696-41de-44c3-89aa-b0aa29f54020
Merrett, Geoffrey
89b3a696-41de-44c3-89aa-b0aa29f54020

Merrett, Geoffrey (2017) CPU power estimation using PMCs and its application in gem5. At ARM Research Summit 2017 ARM Research Summit 2017, Cambridge, United Kingdom. 11 - 13 Sep 2017. (In Press)

Record type: Conference or Workshop Item (Other)

Abstract

Fast and accurate estimation of CPU power consumption is necessary to inform run-time power management approaches and allow effective design space exploration. Power simulators, combined with a full-system architectural simulator such as gem5, enable power-performance trade-offs to be investigated early in the design of a system. However, the accuracy of existing power simulators is known to be low, and this can lead to incorrect conclusions being made. In this talk, I will present our statistically rigorous methodology for building accurate run-time power models using Performance Monitoring Counters (PMCs) for mobile and embedded devices, and demonstrate how our models make more efficient use of limited training data and better adapt to unseen scenarios by uniquely considering stability. Models built using the methodology for both ARM Cortex-A7 and Cortex-A15 CPUs exhibit a 3.8% and 2.8% average error respectively. I will also present online resources that we have made available from the work, including software tools, documentation, raw data and further results. I will also present results from an investigation into the correlation between gem5 activity statistics and hardware PMCs. Based on this, a gem5 power model for a simulated quadcore ARM Cortex-A15 has been created, built using the above methodology, and its accuracy compared against experimental results obtained from hardware.

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More information

Accepted/In Press date: 23 May 2017
Venue - Dates: ARM Research Summit 2017, Cambridge, United Kingdom, 2017-09-11 - 2017-09-13

Identifiers

Local EPrints ID: 412856
URI: https://eprints.soton.ac.uk/id/eprint/412856
PURE UUID: c23fee9a-005b-4170-8139-d0455ff46b15
ORCID for Geoffrey Merrett: ORCID iD orcid.org/0000-0003-4980-3894

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Date deposited: 03 Aug 2017 16:30
Last modified: 06 Jun 2018 12:42

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