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Multi-Path Ageing Sensor for Cost-efficient Delay Fault Prediction

Sai, Gaole, Halak, Basel and Zwolinski, Mark (2017) Multi-Path Ageing Sensor for Cost-efficient Delay Fault Prediction IEEE Transactions on Circuits and Systems Part II: Analog and Digital Signal Processing (doi:10.1109/TCSII.2017.2732028).

Record type: Article


Aggressive technology scaling has accelerated the susceptibility of CMOS devices to aging effects. Consequently, the speed of a path can degrade significantly over time; this results in delay faults. Dynamic reliability management schemes have been proposed to ensure an IC's lifetime reliability. Such schemes are typically based on the use of aging sensors to predict a circuit's failure before errors actually appear. Existing aging sensors are usually placed on the circuit's longest delay paths, which are deemed to be the most vulnerable to delay faults. However, complex designs typically have a large number of long delay paths that need to be monitored. Such approaches are very costly and may be infeasible. This work proposes a new aging sensor, capable of monitoring multiple paths concurrently. The proposed sensor has been designed at transistor level using a 32nm technology and applied to a 32-bit MIPS to monitor 10 paths concurrently. Our results show that using the proposed sensor for monitoring 10 paths can save 197.1% and 97.1% in area overheads compared to Razor and Canary, respectively.

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Accepted/In Press date: 24 July 2017
e-pub ahead of print date: 26 July 2017
Keywords: Delays, ircuit faults, Monitoring, Aging, Circuit stability, Clocks


Local EPrints ID: 413397
ISSN: 1057-7130
PURE UUID: 5e408511-a66e-4652-bf01-c65685e1448f
ORCID for Mark Zwolinski: ORCID iD

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Date deposited: 23 Aug 2017 16:31
Last modified: 23 Aug 2017 16:31

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Author: Gaole Sai
Author: Basel Halak
Author: Mark Zwolinski ORCID iD

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