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BTI mitigation by anti-ageing software patterns

BTI mitigation by anti-ageing software patterns
BTI mitigation by anti-ageing software patterns
This paper presents a time-redundant technique to mitigate Negative and Positive Bias Temperature Instability (NBTI/PBTI) ageing effects on the functional units of a processor. We have analysed the sources and effects of ageing from the device level to the Instruction Set Architecture (ISA) level, and have found that an application may stress the critical paths in such a way that the circuit has half of its nodes always NBTI-stressed. To mitigate this behaviour, we propose an application-level solution to balance the stress and put the timing-critical gates of the critical path into a relaxed (balanced) mode. The results show that the lifetime of the system can be doubled by applying balanced stress patterns at the software level during the idle time of a processor system.
0026-2714
79-90
Abbas, Haider Muhi
df25f48a-4b00-4913-8456-d80a0c31ac10
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Abbas, Haider Muhi, Halak, Basel and Zwolinski, Mark (2017) BTI mitigation by anti-ageing software patterns Microelectronics Reliability, 79, (12), pp. 79-90.

Abbas, Haider Muhi, Halak, Basel and Zwolinski, Mark (2017) BTI mitigation by anti-ageing software patterns Microelectronics Reliability, 79, (12), pp. 79-90.

Record type: Article

Abstract

This paper presents a time-redundant technique to mitigate Negative and Positive Bias Temperature Instability (NBTI/PBTI) ageing effects on the functional units of a processor. We have analysed the sources and effects of ageing from the device level to the Instruction Set Architecture (ISA) level, and have found that an application may stress the critical paths in such a way that the circuit has half of its nodes always NBTI-stressed. To mitigate this behaviour, we propose an application-level solution to balance the stress and put the timing-critical gates of the critical path into a relaxed (balanced) mode. The results show that the lifetime of the system can be doubled by applying balanced stress patterns at the software level during the idle time of a processor system.

Text ecrc-template - Accepted Manuscript
Restricted to Repository staff only until 22 October 2018.

More information

Accepted/In Press date: 11 October 2017
e-pub ahead of print date: 23 October 2017
Published date: December 2017

Identifiers

Local EPrints ID: 415074
URI: http://eprints.soton.ac.uk/id/eprint/415074
ISSN: 0026-2714
PURE UUID: 4655ad5a-09a7-4bb7-8118-ba74f113647b
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 25 Oct 2017 16:30
Last modified: 31 Oct 2017 16:37

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Contributors

Author: Haider Muhi Abbas
Author: Basel Halak
Author: Mark Zwolinski ORCID iD

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