READ ME File For 'Dataset for "Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations"' Dataset DOI: 10.5258/SOTON/D0311 ReadMe Author: Peter Hailes, University of Southampton This dataset supports the publication: P. Hailes, L. Xu, R. G. Maunder, B. M. Al-Hashimi, and L. Hanzo, “Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations,” IEEE Trans. Circuits Syst. II Express Briefs, 2018. Contents +++++++++ The dataset contains a table of data collected for Figure 4. It exhibits a comparison of fixed-point CNPUs constructed using the proposed Dual-tree topology vs. three alternatives (FwdBwd, Multi-tree, and Min2), for a range of input/output numbers (I), measuring hardware resource requirements (measured in Equivalent Logic Blocks) and maximum operating frequency (fmax, measured in Hz). The data was collected via hardware synthesis by Peter Hailes (ph1g09@soton.ac.uk), ECS, University of Southampton, in 2017. Related projects: XXXXXXXXXXXXXXXXXXXX Dataset available under a CC BY 4.0 licence Publisher: University of Southampton, U.K. Date of publication: February 2018