This dataset supports the article entitled 'Low-Power 3D Integration using Inductive Coupling Links for Neurotechnology Applications' accepted for publication in Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018.

Data Supporting Figures:

Fig. 7 - Operation of the proposed ICL transceiver, with intrinsic level conversion, at 0.64GHz.
Fig. 8 - Operation of the proposed CMOS level shifter implementation in conjunction with a 35um TSV link, at 0.64GHz.
Fig. 10 - Power consumption vs aggregate data-rate for each interface style whilst simulating communication between a 2.5V 180nm analogue BiCMOS die and a 1.2V 65nm LP CMOS digital die.

Data Supporting Tables:

Table II - Extracted electrical parameters for inductor layout.
Table IV - TSV modelling parameters for each TSV array style. Extracted at 1GHz.
Table V - Bandwidth, latency and energy per bit values for ICL and TSV based integration approaches.