Lu, Yue and Kazmierski, Tomasz (2017) Variable-accuracy bit-serial multiplication with row bypassing for ultra low power. The IEEE Nordic Circuits and Systems Conference: NORCHIP and International Symposium of System-on-Chip (SoC), Linkoping, Sweden. 24 - 25 Oct 2017.
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Published date: October 2017
Venue - Dates:
The IEEE Nordic Circuits and Systems Conference: NORCHIP and International Symposium of System-on-Chip (SoC), Linkoping, Sweden, 2017-10-24 - 2017-10-25
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Local EPrints ID: 416260
URI: https://eprints.soton.ac.uk/id/eprint/416260
PURE UUID: a3034ad5-fa87-4652-8bde-75bb7e8de072
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Date deposited: 11 Dec 2017 17:30
Last modified: 13 Mar 2019 19:08
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Contributors
Author:
Yue Lu
Author:
Tomasz Kazmierski
University divisions
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