Variable-accuracy bit-serial multiplication with row bypassing for ultra low power
Variable-accuracy bit-serial multiplication with row bypassing for ultra low power
Lu, Yue
447d3b21-4bd8-498d-bd22-f018566b4604
Kazmierski, Tomasz
a97d7958-40c3-413f-924d-84545216092a
October 2017
Lu, Yue
447d3b21-4bd8-498d-bd22-f018566b4604
Kazmierski, Tomasz
a97d7958-40c3-413f-924d-84545216092a
Lu, Yue and Kazmierski, Tomasz
(2017)
Variable-accuracy bit-serial multiplication with row bypassing for ultra low power.
The IEEE Nordic Circuits and Systems Conference: NORCHIP and International Symposium of System-on-Chip (SoC), Linkoping, Sweden.
24 - 25 Oct 2017.
Record type:
Conference or Workshop Item
(Paper)
Full text not available from this repository.
More information
Published date: October 2017
Venue - Dates:
The IEEE Nordic Circuits and Systems Conference: NORCHIP and International Symposium of System-on-Chip (SoC), Linkoping, Sweden, 2017-10-24 - 2017-10-25
Identifiers
Local EPrints ID: 416260
URI: https://eprints.soton.ac.uk/id/eprint/416260
PURE UUID: a3034ad5-fa87-4652-8bde-75bb7e8de072
Catalogue record
Date deposited: 11 Dec 2017 17:30
Last modified: 13 Mar 2019 19:08
Export record
Contributors
Author:
Yue Lu
Author:
Tomasz Kazmierski
University divisions
Download statistics
Downloads from ePrints over the past year. Other digital versions may also be available to download e.g. from the publisher's website.
View more statistics