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Hardware-efficient node processing unit architectures for flexible LDPC decoder implementations

Hardware-efficient node processing unit architectures for flexible LDPC decoder implementations
Hardware-efficient node processing unit architectures for flexible LDPC decoder implementations
In LDPC decoder implementations, the architecture of the Node Processing Units (NPUs) has a significant impact both on the hardware resource requirements and on the processing throughput. Additionally, some NPU architectures impose limitations on the decoder’s support for intra- or inter-standard LDPC code flexibility at run-time. In this paper, we present a generalised algorithmic method of constructing NPUs that support run-time flexibility whilst maintaining a low hardware resource requirement and high maximum operating frequency. FPGA-based synthesis results demonstrate that the proposed architecture offers a significantly improved hardware efficiency, when compared to two commonly-employed alternatives.
1-6
Hailes, Peter
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Xu, Lei
2bb029a5-26b2-495c-976a-7e13e38ec709
Maunder, Robert
76099323-7d58-4732-a98f-22a662ccba6c
Al-Hashimi, Bashir
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Hanzo, Lajos
66e7266f-3066-4fc0-8391-e000acce71a1
Hailes, Peter
deab6991-13c5-4e83-b185-fef11f174421
Xu, Lei
2bb029a5-26b2-495c-976a-7e13e38ec709
Maunder, Robert
76099323-7d58-4732-a98f-22a662ccba6c
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Hanzo, Lajos
66e7266f-3066-4fc0-8391-e000acce71a1

Hailes, Peter, Xu, Lei, Maunder, Robert, Al-Hashimi, Bashir and Hanzo, Lajos (2018) Hardware-efficient node processing unit architectures for flexible LDPC decoder implementations. IEEE Transactions on Circuits and Systems II: Express Briefs, 1-6. (doi:10.1109/TCSII.2018.2807362).

Record type: Article

Abstract

In LDPC decoder implementations, the architecture of the Node Processing Units (NPUs) has a significant impact both on the hardware resource requirements and on the processing throughput. Additionally, some NPU architectures impose limitations on the decoder’s support for intra- or inter-standard LDPC code flexibility at run-time. In this paper, we present a generalised algorithmic method of constructing NPUs that support run-time flexibility whilst maintaining a low hardware resource requirement and high maximum operating frequency. FPGA-based synthesis results demonstrate that the proposed architecture offers a significantly improved hardware efficiency, when compared to two commonly-employed alternatives.

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Accepted/In Press date: 7 February 2018
e-pub ahead of print date: 16 February 2018

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Local EPrints ID: 418176
URI: http://eprints.soton.ac.uk/id/eprint/418176
PURE UUID: c5750737-8df8-40f1-9075-a19fe6599533
ORCID for Peter Hailes: ORCID iD orcid.org/0000-0002-0995-7947
ORCID for Robert Maunder: ORCID iD orcid.org/0000-0002-7944-2615
ORCID for Lajos Hanzo: ORCID iD orcid.org/0000-0002-2636-5214

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Date deposited: 23 Feb 2018 17:30
Last modified: 07 Oct 2020 01:55

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Contributors

Author: Peter Hailes ORCID iD
Author: Lei Xu
Author: Robert Maunder ORCID iD
Author: Bashir Al-Hashimi
Author: Lajos Hanzo ORCID iD

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