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Wafer scale spatially selective transfer of 2D materials and heterostructures

Wafer scale spatially selective transfer of 2D materials and heterostructures
Wafer scale spatially selective transfer of 2D materials and heterostructures
The boom in interest in two dimensional materials has led to intense research, increasingly towards the commercialization of this family of materials. Results to date have proved the viability of wafer scale production of 2D materials, nevertheless no technique for controllable large scale 2D heterostructures, which would seamlessly integrate with existing fabrication lines, has been presented. This is however essential for the production of wafer scale photodiodes, pn-diodes, diode logic gates, and other emerging devices.
There are currently two main approaches for creating heterostructures, i) the sequentially epitaxial growth of 2D materials that results in random spatial growth, rendering this approach non-viable for commercial applications [1] and ii) the mechanical assembly technique, where a 2D flake is transferred and aligned to another flake to form just one heterostructure [2].
Here we report a novel method that can achieve wafer scale fabrication of 2D material-based devices. The method is using a lift-off technique for the micro-patterning of TMDCs and graphene layers that are combined to form heterostructures. The low thermal budget of this process makes this method substrate-agnostic hence suitable for fabrication of devices on temperature sensitive materials such as polymers.
The method uses Atomic Layer Deposition (ALD)-grown metal oxides converted by annealing protocols to 2D TMDCs and copper foil CVD - grown graphene as starting materials. The films are transferred to substrates covered with a pre-patterned photoresist layer. Lift off of the photoresist allows the spatially controllable transfer of the 2D materials allowing for sequential steps to produce aligned heterostructures over large areas.
An overview of the process flow will be presented alongside with a examples of 2D heterostructures such as MoS2 field effect transistors, using graphene source and drain contacts. The deposited microstructures are characterized and furthermore analyzed via Raman mapping, SEM, AFM and XPS measurements.

[1] W. S. Mos, Y. Gong, J. Lin, X. Wang, G. Shi, S. Lei, Z. Lin, X. Zou, G. Ye, R. Vajtai, B. I. Yakobson, H. Terrones, M. Terrones, K. Tay, J. Lou, S. T. Pantelides, Z. Liu, W. Zhou, and P. M. Ajayan, “Vertical and in-plane heterostructures from WS2/MoS2 monolayers,” vol. 13, no. September, p. 8, 2014.
[2] W. J. Yu, Z. Li, H. Zhou, Y. Chen, Y. Wang, Y. Huang, and X. Duan, “Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters.,” Nat. Mater., vol. 12, no. 3, pp. 246–52, 2013
Aspiotis, Nikolaos
b32d40f9-0496-464e-bfcc-217f57ca9dc3
Abbas, Omar, Adnan
e7642f73-874e-4d19-a6c0-4753f6cbfcd0
Zeimpekis, Ioannis
a2c354ec-3891-497c-adac-89b3a5d96af0
Mailis, Sakellaris
233e0768-3f8d-430e-8fdf-92e6f4f6a0c4
Sazio, Pier-John
0d6200b5-9947-469a-8e97-9147da8a7158
Huang, Chung-Che
825f7447-6d02-48f6-b95a-fa33da71f106
Hewak, Daniel
87c80070-c101-4f7a-914f-4cc3131e3db0
Aspiotis, Nikolaos
b32d40f9-0496-464e-bfcc-217f57ca9dc3
Abbas, Omar, Adnan
e7642f73-874e-4d19-a6c0-4753f6cbfcd0
Zeimpekis, Ioannis
a2c354ec-3891-497c-adac-89b3a5d96af0
Mailis, Sakellaris
233e0768-3f8d-430e-8fdf-92e6f4f6a0c4
Sazio, Pier-John
0d6200b5-9947-469a-8e97-9147da8a7158
Huang, Chung-Che
825f7447-6d02-48f6-b95a-fa33da71f106
Hewak, Daniel
87c80070-c101-4f7a-914f-4cc3131e3db0

Aspiotis, Nikolaos, Abbas, Omar, Adnan, Zeimpekis, Ioannis, Mailis, Sakellaris, Sazio, Pier-John, Huang, Chung-Che and Hewak, Daniel (2017) Wafer scale spatially selective transfer of 2D materials and heterostructures. MRS Fall Meeting 2017, Boston, United States. 26 Nov - 01 Dec 2017.

Record type: Conference or Workshop Item (Poster)

Abstract

The boom in interest in two dimensional materials has led to intense research, increasingly towards the commercialization of this family of materials. Results to date have proved the viability of wafer scale production of 2D materials, nevertheless no technique for controllable large scale 2D heterostructures, which would seamlessly integrate with existing fabrication lines, has been presented. This is however essential for the production of wafer scale photodiodes, pn-diodes, diode logic gates, and other emerging devices.
There are currently two main approaches for creating heterostructures, i) the sequentially epitaxial growth of 2D materials that results in random spatial growth, rendering this approach non-viable for commercial applications [1] and ii) the mechanical assembly technique, where a 2D flake is transferred and aligned to another flake to form just one heterostructure [2].
Here we report a novel method that can achieve wafer scale fabrication of 2D material-based devices. The method is using a lift-off technique for the micro-patterning of TMDCs and graphene layers that are combined to form heterostructures. The low thermal budget of this process makes this method substrate-agnostic hence suitable for fabrication of devices on temperature sensitive materials such as polymers.
The method uses Atomic Layer Deposition (ALD)-grown metal oxides converted by annealing protocols to 2D TMDCs and copper foil CVD - grown graphene as starting materials. The films are transferred to substrates covered with a pre-patterned photoresist layer. Lift off of the photoresist allows the spatially controllable transfer of the 2D materials allowing for sequential steps to produce aligned heterostructures over large areas.
An overview of the process flow will be presented alongside with a examples of 2D heterostructures such as MoS2 field effect transistors, using graphene source and drain contacts. The deposited microstructures are characterized and furthermore analyzed via Raman mapping, SEM, AFM and XPS measurements.

[1] W. S. Mos, Y. Gong, J. Lin, X. Wang, G. Shi, S. Lei, Z. Lin, X. Zou, G. Ye, R. Vajtai, B. I. Yakobson, H. Terrones, M. Terrones, K. Tay, J. Lou, S. T. Pantelides, Z. Liu, W. Zhou, and P. M. Ajayan, “Vertical and in-plane heterostructures from WS2/MoS2 monolayers,” vol. 13, no. September, p. 8, 2014.
[2] W. J. Yu, Z. Li, H. Zhou, Y. Chen, Y. Wang, Y. Huang, and X. Duan, “Vertically stacked multi-heterostructures of layered materials for logic transistors and complementary inverters.,” Nat. Mater., vol. 12, no. 3, pp. 246–52, 2013

Full text not available from this repository.

More information

Published date: 1 December 2017
Venue - Dates: MRS Fall Meeting 2017, Boston, United States, 2017-11-26 - 2017-12-01

Identifiers

Local EPrints ID: 418612
URI: https://eprints.soton.ac.uk/id/eprint/418612
PURE UUID: 44525b61-35e3-49c4-8e65-6c5b611afef1
ORCID for Omar, Adnan Abbas: ORCID iD orcid.org/0000-0002-3067-5311
ORCID for Sakellaris Mailis: ORCID iD orcid.org/0000-0001-8100-2670
ORCID for Pier-John Sazio: ORCID iD orcid.org/0000-0002-6506-9266
ORCID for Chung-Che Huang: ORCID iD orcid.org/0000-0003-3471-2463
ORCID for Daniel Hewak: ORCID iD orcid.org/0000-0002-2093-5773

Catalogue record

Date deposited: 12 Mar 2018 17:31
Last modified: 14 Mar 2019 01:53

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Contributors

Author: Nikolaos Aspiotis
Author: Omar, Adnan Abbas ORCID iD
Author: Ioannis Zeimpekis
Author: Pier-John Sazio ORCID iD
Author: Chung-Che Huang ORCID iD
Author: Daniel Hewak ORCID iD

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