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Error-free near-threshold adiabatic CMOS logic in the presence of process variation

Error-free near-threshold adiabatic CMOS logic in the presence of process variation
Error-free near-threshold adiabatic CMOS logic in the presence of process variation

This paper provides the first analysis of process variation effect on the adiabatic logic combined with near-threshold operation. One of the significant concerns is whether reliable performance is retained with voltage scaling. We find that typical variations of process parameters do not affect error-free operation at the minimum-energy frequency. Monte Carlo simulations of a 4-bit full adder using ECRL logic with 0.45 V supply voltage show that in the presence of typical process variations, energy consumption of the circuit operating at 25 MHz increases by 10.2% in the worst case while a 100% error-free operation is maintained. The maximum operating frequency (208 MHz) is reduced to nearly half of the nominal value (385 MHz). To further improve the robustness of the adder against process variation, a bit-serial adiabatic adder is considered with an even lower energy consumption per cycle.

1876-1100
103-114
Springer Verlag
Lu, Yue
447d3b21-4bd8-498d-bd22-f018566b4604
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a
Fummi, Franco
Wille, Robert
Lu, Yue
447d3b21-4bd8-498d-bd22-f018566b4604
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a
Fummi, Franco
Wille, Robert

Lu, Yue and Kazmierski, Tom J. (2018) Error-free near-threshold adiabatic CMOS logic in the presence of process variation. Fummi, Franco and Wille, Robert (eds.) In Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2016: Selected Contributions from FDL 2016. vol. 454, Springer Verlag. pp. 103-114 . (doi:10.1007/978-3-319-62920-9_6).

Record type: Conference or Workshop Item (Paper)

Abstract

This paper provides the first analysis of process variation effect on the adiabatic logic combined with near-threshold operation. One of the significant concerns is whether reliable performance is retained with voltage scaling. We find that typical variations of process parameters do not affect error-free operation at the minimum-energy frequency. Monte Carlo simulations of a 4-bit full adder using ECRL logic with 0.45 V supply voltage show that in the presence of typical process variations, energy consumption of the circuit operating at 25 MHz increases by 10.2% in the worst case while a 100% error-free operation is maintained. The maximum operating frequency (208 MHz) is reduced to nearly half of the nominal value (385 MHz). To further improve the robustness of the adder against process variation, a bit-serial adiabatic adder is considered with an even lower energy consumption per cycle.

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More information

Accepted/In Press date: 1 April 2016
e-pub ahead of print date: 11 November 2017
Published date: 2018
Venue - Dates: Forum on specification and Design Languages, FDL 2016, Bremen, Germany, 2016-09-14 - 2016-09-16

Identifiers

Local EPrints ID: 419190
URI: https://eprints.soton.ac.uk/id/eprint/419190
ISSN: 1876-1100
PURE UUID: 56f08d1e-6b29-4e41-96e1-a19c6625a76d

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Date deposited: 06 Apr 2018 16:31
Last modified: 13 Mar 2019 19:21

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Contributors

Author: Yue Lu
Author: Tom J. Kazmierski
Editor: Franco Fummi
Editor: Robert Wille

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