Double data rate interface
Double data rate interface
The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.
US 8283955
9 October 2012
Redman-White, William
d5376167-c925-460f-8e9c-13bffda8e0bf
Redman-White, William
(Inventors)
(2012)
Double data rate interface.
US 8283955.
Abstract
The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.
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Published date: 9 October 2012
Identifiers
Local EPrints ID: 420471
URI: http://eprints.soton.ac.uk/id/eprint/420471
PURE UUID: e4776475-52ad-4763-b2dc-fa22601c1ff6
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Date deposited: 08 May 2018 16:30
Last modified: 15 Mar 2024 19:30
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Contributors
Inventor:
William Redman-White
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