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Language and hardware acceleration backend for graph processing

Language and hardware acceleration backend for graph processing
Language and hardware acceleration backend for graph processing

Graphs are important in many applications however their analysis on conventional computer architectures is generally inefficient because it involves highly irregular access to memory when traversing vertices and edges. As an example, when finding a path from a source vertex to a target one the performance is typically limited by the memory bottleneck whereas the actual computation is trivial. This paper presents a methodology for embedding graphs into silicon, where graph vertices become finite state machines communicating via the graph edges. With this approach many common graph analysis tasks can be performed by propagating signals through the physical graph and measuring signal propagation time using the on-chip clock distribution network. This eliminates the memory bottleneck and allows thousands of vertices to be processed in parallel. We present a domain-specific language for graph description and transformation, and demonstrate how it can be used to translate application graphs into an FPGA board, where they can be analysed up to 1000× faster than on a conventional computer.

1-7
IEEE Computer Society
Mokhov, Andrey
7ad0909b-34e8-4f32-908c-b6406b397776
De Gennaro, Alessandro
8c78f093-4a6b-4e21-90cc-fb90e4a1c8b3
Tarawneh, Ghaith
1b90fbe9-1337-4216-83ba-b01115bf4000
Wray, Jonny
8f1ea9fa-baf5-463b-bd1f-d2c5cc9b0300
Lukyanov, Georgy
3948942d-d0a7-4748-bb1a-d61956e3e73d
Mileiko, Sergey
83a2afc7-8496-45a3-95b7-75a66b2b907c
Scott, Joe
e6edcb6a-2538-4d3a-920b-d64744997c78
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
Brown, Andrew
5c19e523-65ec-499b-9e7c-91522017d7e0
Mokhov, Andrey
7ad0909b-34e8-4f32-908c-b6406b397776
De Gennaro, Alessandro
8c78f093-4a6b-4e21-90cc-fb90e4a1c8b3
Tarawneh, Ghaith
1b90fbe9-1337-4216-83ba-b01115bf4000
Wray, Jonny
8f1ea9fa-baf5-463b-bd1f-d2c5cc9b0300
Lukyanov, Georgy
3948942d-d0a7-4748-bb1a-d61956e3e73d
Mileiko, Sergey
83a2afc7-8496-45a3-95b7-75a66b2b907c
Scott, Joe
e6edcb6a-2538-4d3a-920b-d64744997c78
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
Brown, Andrew
5c19e523-65ec-499b-9e7c-91522017d7e0

Mokhov, Andrey, De Gennaro, Alessandro, Tarawneh, Ghaith, Wray, Jonny, Lukyanov, Georgy, Mileiko, Sergey, Scott, Joe, Yakovlev, Alex and Brown, Andrew (2018) Language and hardware acceleration backend for graph processing. In FDL 2017 - Proceedings of the 2017 Forum on Specification and Design Languages. vol. 2017-September, IEEE Computer Society. pp. 1-7 . (doi:10.1109/FDL.2017.8303899).

Record type: Conference or Workshop Item (Paper)

Abstract

Graphs are important in many applications however their analysis on conventional computer architectures is generally inefficient because it involves highly irregular access to memory when traversing vertices and edges. As an example, when finding a path from a source vertex to a target one the performance is typically limited by the memory bottleneck whereas the actual computation is trivial. This paper presents a methodology for embedding graphs into silicon, where graph vertices become finite state machines communicating via the graph edges. With this approach many common graph analysis tasks can be performed by propagating signals through the physical graph and measuring signal propagation time using the on-chip clock distribution network. This eliminates the memory bottleneck and allows thousands of vertices to be processed in parallel. We present a domain-specific language for graph description and transformation, and demonstrate how it can be used to translate application graphs into an FPGA board, where they can be analysed up to 1000× faster than on a conventional computer.

Full text not available from this repository.

More information

Accepted/In Press date: 18 September 2017
Published date: 27 February 2018
Venue - Dates: 2017 Forum on Specification and Design Languages, FDL 2017, Italy, 2017-09-17 - 2017-09-19

Identifiers

Local EPrints ID: 421196
URI: http://eprints.soton.ac.uk/id/eprint/421196
PURE UUID: bfcb2fab-9409-4029-86c6-8cf8f2b99d70

Catalogue record

Date deposited: 24 May 2018 16:30
Last modified: 06 Oct 2020 21:31

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