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Memory and thread synchronization contention-aware DVFS for HPC systems

Memory and thread synchronization contention-aware DVFS for HPC systems
Memory and thread synchronization contention-aware DVFS for HPC systems
Due to the operating costs and failure rates of computing platforms, energy efficiency has become a major concern for modern and future many-core systems. In the quest for high performance, the power consumption growth rate must slow down while delivering more performance per unit of power. To improve the energy efficiency of such systems, processors are equipped with low-power techniques such as dynamic voltage and frequency scaling (DVFS) and power capping. These techniques must be controlled carefully as per the workload; otherwise, it may result in significant performance loss and/or power consumption due to system overheads (e.g. DVFS transition latency). Existing approaches [1], [2] are not effective in adapting to workload variations as they do not consider the combined effect of application compute-/memory-intensity, thread synchronization contention, and non-uniform memory accesses (NUMAs) owing to the underlying processor architecture. This poster discusses a workload-aware runtime energy management technique that takes the aforementioned factors into account for efficient V-f control.
Basireddy, Karunakar Reddy
5bfb0b2e-8242-499a-a52b-e813d9a90889
Weber Wachter, Eduardo
bdacc537-b1ac-4241-a6fc-b67f1e6a6ce8
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Merrett, Geoff
89b3a696-41de-44c3-89aa-b0aa29f54020
Basireddy, Karunakar Reddy
5bfb0b2e-8242-499a-a52b-e813d9a90889
Weber Wachter, Eduardo
bdacc537-b1ac-4241-a6fc-b67f1e6a6ce8
Al-Hashimi, Bashir
0b29c671-a6d2-459c-af68-c4614dce3b5d
Merrett, Geoff
89b3a696-41de-44c3-89aa-b0aa29f54020

Basireddy, Karunakar Reddy, Weber Wachter, Eduardo, Al-Hashimi, Bashir and Merrett, Geoff (2018) Memory and thread synchronization contention-aware DVFS for HPC systems. Adaptive Many-Core Architectures and Systems workshop, York, United Kingdom. 13 - 15 Jun 2018. 1 pp.

Record type: Conference or Workshop Item (Other)

Abstract

Due to the operating costs and failure rates of computing platforms, energy efficiency has become a major concern for modern and future many-core systems. In the quest for high performance, the power consumption growth rate must slow down while delivering more performance per unit of power. To improve the energy efficiency of such systems, processors are equipped with low-power techniques such as dynamic voltage and frequency scaling (DVFS) and power capping. These techniques must be controlled carefully as per the workload; otherwise, it may result in significant performance loss and/or power consumption due to system overheads (e.g. DVFS transition latency). Existing approaches [1], [2] are not effective in adapting to workload variations as they do not consider the combined effect of application compute-/memory-intensity, thread synchronization contention, and non-uniform memory accesses (NUMAs) owing to the underlying processor architecture. This poster discusses a workload-aware runtime energy management technique that takes the aforementioned factors into account for efficient V-f control.

Text ManyCoreWorkshop - 1page - Accepted Manuscript
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More information

Published date: 1 June 2018
Venue - Dates: Adaptive Many-Core Architectures and Systems workshop, York, United Kingdom, 2018-06-13 - 2018-06-15

Identifiers

Local EPrints ID: 421526
URI: https://eprints.soton.ac.uk/id/eprint/421526
PURE UUID: 2b6e4911-6b71-43ec-994e-5315584806d1
ORCID for Karunakar Reddy Basireddy: ORCID iD orcid.org/0000-0001-9755-1041
ORCID for Geoff Merrett: ORCID iD orcid.org/0000-0003-4980-3894

Catalogue record

Date deposited: 14 Jun 2018 16:30
Last modified: 15 Jun 2018 00:32

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