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Flip-flop

Flip-flop
Flip-flop
A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.
flip-flops, ASIC design, electrical
US9985613B2
Cai, Yunpeng
dbb0299d-11fa-416f-8785-095704dea862
Savanth, Parameshwarappa Anand, Kumar
57b60ac8-bbb6-4517-9d5e-668d82500190
Myers, James
b541d1fd-a24a-4771-91b3-84e1ac8c7fe5
Weddell, Alexander
3d8c4d63-19b1-4072-a779-84d487fd6f03
Kazmierski, Tomasz
a97d7958-40c3-413f-924d-84545216092a

Cai, Yunpeng, Savanth, Parameshwarappa Anand, Kumar, Myers, James, Weddell, Alexander and Kazmierski, Tomasz (Inventors) (2018) Flip-flop. US9985613B2.

Record type: Patent

Abstract

A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.

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US9985613 - Version of Record
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More information

Published date: 29 May 2018
Keywords: flip-flops, ASIC design, electrical

Identifiers

Local EPrints ID: 421646
URI: https://eprints.soton.ac.uk/id/eprint/421646
PURE UUID: 2dfa4e2d-fb59-4317-8385-1f51775d4342
ORCID for Yunpeng Cai: ORCID iD orcid.org/0000-0003-2832-6750
ORCID for Alexander Weddell: ORCID iD orcid.org/0000-0002-6763-5460

Catalogue record

Date deposited: 11 Oct 2018 16:30
Last modified: 17 May 2019 00:27

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Contributors

Inventor: Yunpeng Cai ORCID iD
Inventor: Parameshwarappa Anand, Kumar Savanth
Inventor: James Myers
Inventor: Alexander Weddell ORCID iD
Inventor: Tomasz Kazmierski

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