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Lifetime reliability-aware digital synthesis

Lifetime reliability-aware digital synthesis
Lifetime reliability-aware digital synthesis
CMOS downscaling poses a growing concern for circuit lifetime reliability. Bias Temperature Instability (BTI) is a major source of transistor aging, causing a threshold voltage increase in CMOS devices and affecting circuit timing. This paper presents an aging mitigation approach that can be incorporated in standard synthesis. We propose a technique to restructure the logic expressions for aging-critical gates and to reduce the BTI stress duty cycle. A new technology mapping strategy is demonstrated, including a forward pass to select the proper cells and implement the optimized logic, and a backward pass to validate remapped circuits by restricting the negative slacks. The negative slacks produced in the mapping stage are eliminated by gate-level optimization, which aims to optimize a circuit to improve lifetime reliability under timing and area constraints. It employs a sensitivity metric that can be adjusted according to the design specifications to pick the most favorable transformation in terms of timing, lifetime or both. Our results show a 59.1% lifetime improvement with 0.86% area overhead on average. Compared with conventional over-design, a 28.29% higher lifetime improvement is realized. In addition, our approach can optimize a circuit under each corner case, considering both process variations and input data.
1063-8210
1-12
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33

Duan, Shengyu, Zwolinski, Mark and Halak, Basel (2018) Lifetime reliability-aware digital synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1-12. (doi:10.1109/TVLSI.2018.2861820).

Record type: Article

Abstract

CMOS downscaling poses a growing concern for circuit lifetime reliability. Bias Temperature Instability (BTI) is a major source of transistor aging, causing a threshold voltage increase in CMOS devices and affecting circuit timing. This paper presents an aging mitigation approach that can be incorporated in standard synthesis. We propose a technique to restructure the logic expressions for aging-critical gates and to reduce the BTI stress duty cycle. A new technology mapping strategy is demonstrated, including a forward pass to select the proper cells and implement the optimized logic, and a backward pass to validate remapped circuits by restricting the negative slacks. The negative slacks produced in the mapping stage are eliminated by gate-level optimization, which aims to optimize a circuit to improve lifetime reliability under timing and area constraints. It employs a sensitivity metric that can be adjusted according to the design specifications to pick the most favorable transformation in terms of timing, lifetime or both. Our results show a 59.1% lifetime improvement with 0.86% area overhead on average. Compared with conventional over-design, a 28.29% higher lifetime improvement is realized. In addition, our approach can optimize a circuit under each corner case, considering both process variations and input data.

Text
Shengyu_Journal_final - Accepted Manuscript
Restricted to Repository staff only until 18 October 2018.
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More information

Submitted date: 2018
Accepted/In Press date: 18 July 2018
e-pub ahead of print date: 13 August 2018

Identifiers

Local EPrints ID: 421690
URI: https://eprints.soton.ac.uk/id/eprint/421690
ISSN: 1063-8210
PURE UUID: c0ad89be-8d6d-445a-b190-b2554ac7f151
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226

Catalogue record

Date deposited: 21 Jun 2018 16:30
Last modified: 17 Jul 2019 01:20

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