Hardware implementation of a low-power K-Best MIMO detector based on a hybrid merge network
Hardware implementation of a low-power K-Best MIMO detector based on a hybrid merge network
Multiple input multiple output (MIMO) technology is anticipated to play a key role in future wireless communications systems. However, one of the main challenges of MIMO technology is the high complexity of the signal detection, which results in a high power consumption at the MIMO receiver. In this paper, we present the hardware implementation of a K-Best detector based on a single-stage architecture, targeted at low-rate and low-power applications. To achieve a low complexity, we optimise the sorting stage of the detector by systematically eliminating redundant comparators. Furthermore, the sorter incorporates different merge algorithms at selected stages in order to reduce the total comparator count. For a 64-QAM 4x4 MIMO system, the detector achieves a power consumption of 34 mW using the STMicroelectronics 65nm CMOS library, which compares favourably with similar works from the literature.
Bello, Ibrahim A.
23297306-2748-4352-9c82-c9cec77b06fc
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
El-Hajjar, Mohammed
3a829028-a427-4123-b885-2bab81a44b6f
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
July 2018
Bello, Ibrahim A.
23297306-2748-4352-9c82-c9cec77b06fc
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
El-Hajjar, Mohammed
3a829028-a427-4123-b885-2bab81a44b6f
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Bello, Ibrahim A., Halak, Basel, El-Hajjar, Mohammed and Zwolinski, Mark
(2018)
Hardware implementation of a low-power K-Best MIMO detector based on a hybrid merge network.
In 2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).
IEEE..
(doi:10.1109/PATMOS.2018.8464169).
Record type:
Conference or Workshop Item
(Paper)
Abstract
Multiple input multiple output (MIMO) technology is anticipated to play a key role in future wireless communications systems. However, one of the main challenges of MIMO technology is the high complexity of the signal detection, which results in a high power consumption at the MIMO receiver. In this paper, we present the hardware implementation of a K-Best detector based on a single-stage architecture, targeted at low-rate and low-power applications. To achieve a low complexity, we optimise the sorting stage of the detector by systematically eliminating redundant comparators. Furthermore, the sorter incorporates different merge algorithms at selected stages in order to reduce the total comparator count. For a 64-QAM 4x4 MIMO system, the detector achieves a power consumption of 34 mW using the STMicroelectronics 65nm CMOS library, which compares favourably with similar works from the literature.
Text
PATMOS paper
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Accepted/In Press date: 25 April 2018
Published date: July 2018
Venue - Dates:
28th International Symposium on Power and Timing Modeling, Optimization and Simulation, Spain, 2018-07-02 - 2018-07-04
Identifiers
Local EPrints ID: 421988
URI: http://eprints.soton.ac.uk/id/eprint/421988
PURE UUID: 2864af62-8e73-4545-a1fd-e23a3960f695
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Date deposited: 12 Jul 2018 16:30
Last modified: 16 Mar 2024 04:10
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