READ ME File For 'Lifetime Reliability-aware Digital Synthesis'

Dataset DOI: 10.5258/SOTON/D0559

ReadMe Author: Shengyu Duan, University of Southampton

This dataset supports the publication:
Shengyu Duan, Mark Zwolinski, and Basel Halak
Lifetime Reliability-aware Digital Synthesis
IEEE Transcations on Very Large Scale Integration (VLSI) Systems


This dataset contains:

Data supporting lifetime reliability-aware digital synthesis experiments and simulations, including Table III Nominal case circuit performances by the proposed approaches and Table IV Nominal case lifetime reliability by conventional over-design and our approach. 
Source codes of the programs of BTI lifetime optimizations and analysis


The figures are as follows:

Fig. 2  10 year degradation in c432 circuit with different input patterns
Fig. 7  Degradation decrease by proposed approaches on c880
Fig. 8  Lifetime increase by proposed approaches on c880


Date of data collection: August 2017

Information about geographic location of data collection: University of Southampton, U.K.

Related projects:
An Ageing-aware Digital Synthesis Approach


Date that the file was created: July 2018