Hybrid cascaded multilevel inverter (HCMLI) with improved symmetrical 4-level submodule
Hybrid cascaded multilevel inverter (HCMLI) with improved symmetrical 4-level submodule
This letter proposes an improved symmetrical 4-level submodule as a basic cell for generating multiple dc voltage levels. A hybrid cascaded multilevel inverter (HCMLI) topology is formed by the combination of n submodules and a full-bridge. A comparative analysis against the recent multilevel inverters reveals that the proposed topology requires less number of switches and dc sources. In addition, the proposed submodule reduces the number of conducting switch and gate driver requirements compared to the widely used half-bridge submodule. To validate the operation of the proposed HCMLI topology, experimental results of a 9-level single-phase inverter controlled by selective harmonic elimination pulse-width-modulation is presented.
Hybrid cascaded multilevel inverter (HCMLI), reduced switch count, symmetrical submodule
932-935
Lee, Sze Sing
47f36964-db27-4f5e-a4d3-4b0ba78ce29e
Sidorov, Michail
0b790317-f69d-4156-8c66-4527086fafc9
Lim, Chee Shen
616d0697-a5d5-4079-adaa-6686e5a758fe
Idris, Nik Rumzi Nik
45b54a20-e821-402c-9ac9-fcd9e82e3598
Heng, Yeh En
6860b43b-9bb5-4553-901f-397d71801b4b
February 2018
Lee, Sze Sing
47f36964-db27-4f5e-a4d3-4b0ba78ce29e
Sidorov, Michail
0b790317-f69d-4156-8c66-4527086fafc9
Lim, Chee Shen
616d0697-a5d5-4079-adaa-6686e5a758fe
Idris, Nik Rumzi Nik
45b54a20-e821-402c-9ac9-fcd9e82e3598
Heng, Yeh En
6860b43b-9bb5-4553-901f-397d71801b4b
Lee, Sze Sing, Sidorov, Michail, Lim, Chee Shen, Idris, Nik Rumzi Nik and Heng, Yeh En
(2018)
Hybrid cascaded multilevel inverter (HCMLI) with improved symmetrical 4-level submodule.
IEEE Transactions on Power Electronics, 33 (2), .
(doi:10.1109/TPEL.2017.2726087).
Abstract
This letter proposes an improved symmetrical 4-level submodule as a basic cell for generating multiple dc voltage levels. A hybrid cascaded multilevel inverter (HCMLI) topology is formed by the combination of n submodules and a full-bridge. A comparative analysis against the recent multilevel inverters reveals that the proposed topology requires less number of switches and dc sources. In addition, the proposed submodule reduces the number of conducting switch and gate driver requirements compared to the widely used half-bridge submodule. To validate the operation of the proposed HCMLI topology, experimental results of a 9-level single-phase inverter controlled by selective harmonic elimination pulse-width-modulation is presented.
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More information
Accepted/In Press date: 8 July 2017
e-pub ahead of print date: 12 July 2017
Published date: February 2018
Keywords:
Hybrid cascaded multilevel inverter (HCMLI), reduced switch count, symmetrical submodule
Identifiers
Local EPrints ID: 423006
URI: http://eprints.soton.ac.uk/id/eprint/423006
ISSN: 0885-8993
PURE UUID: 20708e2e-cd9b-438e-b965-9a83343f7c6a
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Date deposited: 09 Aug 2018 16:30
Last modified: 15 Mar 2024 21:10
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Contributors
Author:
Sze Sing Lee
Author:
Michail Sidorov
Author:
Chee Shen Lim
Author:
Nik Rumzi Nik Idris
Author:
Yeh En Heng
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