Conceiving extrinsic information transfer charts for stochastic low-density parity-check decoders
Conceiving extrinsic information transfer charts for stochastic low-density parity-check decoders
Stochastic Low-Density Parity-Check Decoders (SLDPC) have found favour recently both for correcting transmission errors as well as for improving the hardware efficiency. The main drawback of these decoders is that they require hundreds of time periods to decode each frame, but their chip-area is smaller than that of their fixed point counterparts, so they can achieve higher hardware efficiency and may consume less energy. In this paper we propose a novel EXIT chart technique for characterizing the iterative decoding convergence of all the sequences involved in the Stochastic Low-Density Parity-Check Decoder. We have conceived a new model, which takes into consideration not only the sequences exchanged between the decoders, but also the sequences generated inside the variable node decoder (those which are stored in the edge memories). In this way, the model is able to predict the number of decoding iterations required for achieving iterative decoding convergence, as confirmed by own decoder simulations. The proposed technique offers new insights into the operation of SLDPCs, which will facilitate improved designs for the research community.
55741-55753
Pérez-Pascual, Asun
480c6161-d9db-4322-ab31-683ee0ad0f52
Hamilton, Alexander, James Beaumont
73418485-6e91-4151-9a21-d6219807a2d7
Maunder, Robert
76099323-7d58-4732-a98f-22a662ccba6c
Hanzo, Lajos
66e7266f-3066-4fc0-8391-e000acce71a1
26 September 2018
Pérez-Pascual, Asun
480c6161-d9db-4322-ab31-683ee0ad0f52
Hamilton, Alexander, James Beaumont
73418485-6e91-4151-9a21-d6219807a2d7
Maunder, Robert
76099323-7d58-4732-a98f-22a662ccba6c
Hanzo, Lajos
66e7266f-3066-4fc0-8391-e000acce71a1
Pérez-Pascual, Asun, Hamilton, Alexander, James Beaumont, Maunder, Robert and Hanzo, Lajos
(2018)
Conceiving extrinsic information transfer charts for stochastic low-density parity-check decoders.
IEEE Access, 6, .
(doi:10.1109/ACCESS.2018.2872113).
Abstract
Stochastic Low-Density Parity-Check Decoders (SLDPC) have found favour recently both for correcting transmission errors as well as for improving the hardware efficiency. The main drawback of these decoders is that they require hundreds of time periods to decode each frame, but their chip-area is smaller than that of their fixed point counterparts, so they can achieve higher hardware efficiency and may consume less energy. In this paper we propose a novel EXIT chart technique for characterizing the iterative decoding convergence of all the sequences involved in the Stochastic Low-Density Parity-Check Decoder. We have conceived a new model, which takes into consideration not only the sequences exchanged between the decoders, but also the sequences generated inside the variable node decoder (those which are stored in the edge memories). In this way, the model is able to predict the number of decoding iterations required for achieving iterative decoding convergence, as confirmed by own decoder simulations. The proposed technique offers new insights into the operation of SLDPCs, which will facilitate improved designs for the research community.
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e-pub ahead of print date: 26 September 2018
Published date: 26 September 2018
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Local EPrints ID: 423720
URI: http://eprints.soton.ac.uk/id/eprint/423720
ISSN: 2169-3536
PURE UUID: 80c4211a-2e04-4dda-88a4-16e8b76b97aa
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Date deposited: 28 Sep 2018 16:30
Last modified: 18 Mar 2024 03:35
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