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Ultra-low power 18-transistor fully-static contention-free single-phase clocked flip-flop in 65nm CMOS

Ultra-low power 18-transistor fully-static contention-free single-phase clocked flip-flop in 65nm CMOS
Ultra-low power 18-transistor fully-static contention-free single-phase clocked flip-flop in 65nm CMOS
Flip-flops are essential building blocks of sequential digital circuits, but typically occupy a substantial proportion of chip area and consume significant amounts of power. This work proposes 18TSPC, a new topology of fully-static contention-free Single-Phase Clocked (SPC) Flip-Flop (FF) with only 18 transistors, the lowest number reported for this type. Implemented in 65nm CMOS, it achieves 20% cell area reduction compared to the conventional Transmission Gate FF (TGFF). Simulation results show the proposed 18TSPC is 3 times more efficient than TGFF in the Energy-Delay space. To demonstrate EDA compatibility and circuit/system-level benefits, a shift-register and an AES-128 encryption engine have been implemented. Chip experimental measurements at 0.6V, 25ºC show that, compared to TGFF, the proposed 18TSPC achieves reductions of 68% and 73% in overall and clock dynamic power, respectively, and 27% lower leakage.
ultra-low power, single-phase clocked, flip-flops
0018-9200
1-10
Cai, Yunpeng
dbb0299d-11fa-416f-8785-095704dea862
Savanth, Parameshwarappa Anand Kumar
57b60ac8-bbb6-4517-9d5e-668d82500190
Prabhat, Pranay
6d246b81-a756-431c-865c-2f58e0d03008
Myers, James
b541d1fd-a24a-4771-91b3-84e1ac8c7fe5
Weddell, Alexander
3d8c4d63-19b1-4072-a779-84d487fd6f03
Kazmierski, Tomasz
a97d7958-40c3-413f-924d-84545216092a
Cai, Yunpeng
dbb0299d-11fa-416f-8785-095704dea862
Savanth, Parameshwarappa Anand Kumar
57b60ac8-bbb6-4517-9d5e-668d82500190
Prabhat, Pranay
6d246b81-a756-431c-865c-2f58e0d03008
Myers, James
b541d1fd-a24a-4771-91b3-84e1ac8c7fe5
Weddell, Alexander
3d8c4d63-19b1-4072-a779-84d487fd6f03
Kazmierski, Tomasz
a97d7958-40c3-413f-924d-84545216092a

Cai, Yunpeng, Savanth, Parameshwarappa Anand Kumar, Prabhat, Pranay, Myers, James, Weddell, Alexander and Kazmierski, Tomasz (2018) Ultra-low power 18-transistor fully-static contention-free single-phase clocked flip-flop in 65nm CMOS. IEEE Journal of Solid State Circuits, 1-10. (doi:10.1109/JSSC.2018.2875089).

Record type: Article

Abstract

Flip-flops are essential building blocks of sequential digital circuits, but typically occupy a substantial proportion of chip area and consume significant amounts of power. This work proposes 18TSPC, a new topology of fully-static contention-free Single-Phase Clocked (SPC) Flip-Flop (FF) with only 18 transistors, the lowest number reported for this type. Implemented in 65nm CMOS, it achieves 20% cell area reduction compared to the conventional Transmission Gate FF (TGFF). Simulation results show the proposed 18TSPC is 3 times more efficient than TGFF in the Energy-Delay space. To demonstrate EDA compatibility and circuit/system-level benefits, a shift-register and an AES-128 encryption engine have been implemented. Chip experimental measurements at 0.6V, 25ºC show that, compared to TGFF, the proposed 18TSPC achieves reductions of 68% and 73% in overall and clock dynamic power, respectively, and 27% lower leakage.

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JSSC cai final - Accepted Manuscript
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More information

Accepted/In Press date: 5 October 2018
e-pub ahead of print date: 26 October 2018
Keywords: ultra-low power, single-phase clocked, flip-flops

Identifiers

Local EPrints ID: 425028
URI: https://eprints.soton.ac.uk/id/eprint/425028
ISSN: 0018-9200
PURE UUID: fc5401ba-afe4-4164-ba14-4a084ca68bb6
ORCID for Yunpeng Cai: ORCID iD orcid.org/0000-0003-2832-6750
ORCID for Alexander Weddell: ORCID iD orcid.org/0000-0002-6763-5460

Catalogue record

Date deposited: 09 Oct 2018 16:30
Last modified: 10 Dec 2019 01:43

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