READ ME File For 'Dataset for 'Ultra-Low Power 18-Transistor Fully-Static Contention-Free Single-Phase Clocked Flip-Flop in 65nm CMOS'

Dataset DOI: 10.5258/SOTON/D0678

Readme author: Yunpeng Cai, University of Southampton

This dataset supports the article entitled "Ultra-Low Power 18-Transistor Fully-Static Contention-Free Single-Phase Clocked Flip-Flop in 65nm CMOS" 
accepted for publication in IEEE Journal of Solid State Circuits, October 2018

Data Supporting Figures:
in Date_set:
Fig 8 - Normalized Energy/cycle with activity rate= 100% at nominal supply voltage
(1.2V for 65nm CMOS, 1.0V for 45nm FDSOI [9]) and NTV (0.6V for 65nm
CMOS, 0.4V for 45nm FDSOI [9].

Fig 9 - 10K Monte-Carlo simulation results of D-to-Q Delay.

Fig 13b - Measured power of 320-bit Shift-Reg against activity rate at  (b) 0.6V with 25C

Fig 14 - Measured total power of 320-bit Shift-Reg with (a) activity rate = 100% (b)
activity rate = 0% with fixed clock frequency (FBoard MAX = 66 MHz) at different
supply voltage.

Fig 15 - Measured results of the 18TSPC AES-128 block (Typical Die).

Fig 16 - Vmin distribution of Shift-Reg over 92 test chips.

Fig 17 - Functional Vmin of AES-128 block and Shift-Reg with 0.1 MHz
clock frequency at different temperature condition.

text data:
P4_007_B22_0C1p2V66MHz_2018125_141242_AS - measurement at 1.2V/66MHz/0C
P4_007_B22_25C1p2V66MHz_2018125_122931_AS - measurement at 1.2V/66MHz/25C
P4_007_B22_85C1p2V66MHz_2018125_153335_AS - measurement at 1.2V/66MHz/85C
which support the Fig 13a



Geographic location of data collection: University of Southampton, U.K.


Dataset available under a CC BY 4.0 licence


Publisher: University of Southampton, U.K.


Date: October 2018