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Workload-Aware runtime energy management for HPC Systems

Workload-Aware runtime energy management for HPC Systems
Workload-Aware runtime energy management for HPC Systems

Energy efficiency has become a crucial factor in high-performance computing, mainly due to its effect on operating costs and failure rates of computing platforms. To improve the energy efficiency of such systems, processors are equipped with low-power techniques such as dynamic voltage and frequency scaling (DVFS) and power capping. These techniques have to be controlled carefully as per the workload; otherwise, it may result in significant performance loss and/or power consumption due to system overheads (e.g. DVFS transition latency). Existing approaches are not effective in adapting to workload variations as they do not consider the combined effect of application compute-/memory-intensity, thread synchronization contention, and nonuniform memory accesses (NUMAs) owing to the underlying processor architecture. In this work, we propose a workload-aware runtime energy management technique that takes the aforementioned factors into account for efficient V-f control. The proposed technique measures the processor workload using Memory Accesses Per Micro-operation (MAPM), and also considers the thread synchronization contention and latency due to NUMAs to select an appropriate V-f setting. This approach also uses workload prediction for pro-Active V-f control to improve the energy consumption and performance loss. The proposed technique has been implemented on the 12-core (24 threads) Intel Xeon E5-2630 and 61-core (244 threads) Xeon Phi many-core platforms, supporting per-core and system-wide DVFS, respectively. When evaluated with different application scenarios, results show an improvement in energy efficiency of up to 81.2% compared to existing approaches.

Dynamic Voltage and Frequency Scaling, High-Performance Computing, Non-Uniform Memory Access, Run-Time Power/Energy Management
292-299
Institute of Electrical and Electronics Engineers Inc.
Reddy Basireddy, Karunakar
5bfb0b2e-8242-499a-a52b-e813d9a90889
Wachter, Eduardo Weber
bdacc537-b1ac-4241-a6fc-b67f1e6a6ce8
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Merrett, Geoff
89b3a696-41de-44c3-89aa-b0aa29f54020
Reddy Basireddy, Karunakar
5bfb0b2e-8242-499a-a52b-e813d9a90889
Wachter, Eduardo Weber
bdacc537-b1ac-4241-a6fc-b67f1e6a6ce8
Al-Hashimi, Bashir M.
0b29c671-a6d2-459c-af68-c4614dce3b5d
Merrett, Geoff
89b3a696-41de-44c3-89aa-b0aa29f54020

Reddy Basireddy, Karunakar, Wachter, Eduardo Weber, Al-Hashimi, Bashir M. and Merrett, Geoff (2018) Workload-Aware runtime energy management for HPC Systems. In Proceedings - 2018 International Conference on High Performance Computing and Simulation, HPCS 2018. Institute of Electrical and Electronics Engineers Inc. pp. 292-299 . (doi:10.1109/HPCS.2018.00057).

Record type: Conference or Workshop Item (Paper)

Abstract

Energy efficiency has become a crucial factor in high-performance computing, mainly due to its effect on operating costs and failure rates of computing platforms. To improve the energy efficiency of such systems, processors are equipped with low-power techniques such as dynamic voltage and frequency scaling (DVFS) and power capping. These techniques have to be controlled carefully as per the workload; otherwise, it may result in significant performance loss and/or power consumption due to system overheads (e.g. DVFS transition latency). Existing approaches are not effective in adapting to workload variations as they do not consider the combined effect of application compute-/memory-intensity, thread synchronization contention, and nonuniform memory accesses (NUMAs) owing to the underlying processor architecture. In this work, we propose a workload-aware runtime energy management technique that takes the aforementioned factors into account for efficient V-f control. The proposed technique measures the processor workload using Memory Accesses Per Micro-operation (MAPM), and also considers the thread synchronization contention and latency due to NUMAs to select an appropriate V-f setting. This approach also uses workload prediction for pro-Active V-f control to improve the energy consumption and performance loss. The proposed technique has been implemented on the 12-core (24 threads) Intel Xeon E5-2630 and 61-core (244 threads) Xeon Phi many-core platforms, supporting per-core and system-wide DVFS, respectively. When evaluated with different application scenarios, results show an improvement in energy efficiency of up to 81.2% compared to existing approaches.

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More information

Published date: 29 October 2018
Venue - Dates: 16th International Conference on High Performance Computing and Simulation, HPCS 2018, Orleans, France, 2018-07-16 - 2018-07-20
Keywords: Dynamic Voltage and Frequency Scaling, High-Performance Computing, Non-Uniform Memory Access, Run-Time Power/Energy Management

Identifiers

Local EPrints ID: 426986
URI: https://eprints.soton.ac.uk/id/eprint/426986
PURE UUID: 783186ff-ac5d-4603-92cc-67932157936b
ORCID for Karunakar Reddy Basireddy: ORCID iD orcid.org/0000-0001-9755-1041
ORCID for Geoff Merrett: ORCID iD orcid.org/0000-0003-4980-3894

Catalogue record

Date deposited: 20 Dec 2018 17:30
Last modified: 14 Mar 2019 01:42

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Contributors

Author: Karunakar Reddy Basireddy ORCID iD
Author: Eduardo Weber Wachter
Author: Geoff Merrett ORCID iD

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