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A machine learning attacks resistant two stage physical unclonable functions design

A machine learning attacks resistant two stage physical unclonable functions design
A machine learning attacks resistant two stage physical unclonable functions design

Physical Unclonable Functions (PUFs) have been designed for many security applications such as identification, authentication of devices and key generation, especially for lightweight electronics. Traditional approaches to enhancing security, such as hash functions, may be expensive and resource dependent. However, modelling attacks using machine learning (ML) show the vulnerability of most PUFs. In this paper, a combination of a 32-bit current mirror and 16-bit arbiter PUFs in 65nm CMOS technology is proposed to improve resilience against modelling attacks. Both PUFs are vulnerable to machine learning attacks and we reduce the output prediction rate from 99.2% and 98.8% individually, to 60%.

Arbiter-PUF, Current Mirror PUF, Machine Learning, Physical Unclonable Function (PUF), Security
52-55
Institute of Electrical and Electronics Engineers Inc.
Su, Haibo
07117108-5e87-4450-9853-1d4c12d387ca
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Su, Haibo
07117108-5e87-4450-9853-1d4c12d387ca
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33

Su, Haibo, Zwolinski, Mark and Halak, Basel (2018) A machine learning attacks resistant two stage physical unclonable functions design. In 2018 IEEE 3rd International Verification and Security Workshop, IVSW 2018. Institute of Electrical and Electronics Engineers Inc. pp. 52-55 . (doi:10.1109/IVSW.2018.8494839).

Record type: Conference or Workshop Item (Paper)

Abstract

Physical Unclonable Functions (PUFs) have been designed for many security applications such as identification, authentication of devices and key generation, especially for lightweight electronics. Traditional approaches to enhancing security, such as hash functions, may be expensive and resource dependent. However, modelling attacks using machine learning (ML) show the vulnerability of most PUFs. In this paper, a combination of a 32-bit current mirror and 16-bit arbiter PUFs in 65nm CMOS technology is proposed to improve resilience against modelling attacks. Both PUFs are vulnerable to machine learning attacks and we reduce the output prediction rate from 99.2% and 98.8% individually, to 60%.

Full text not available from this repository.

More information

Published date: 16 October 2018
Venue - Dates: 3rd IEEE International Verification and Security Workshop, IVSW 2018, Costa Brava, Spain, 2018-07-02 - 2018-07-04
Keywords: Arbiter-PUF, Current Mirror PUF, Machine Learning, Physical Unclonable Function (PUF), Security

Identifiers

Local EPrints ID: 426990
URI: https://eprints.soton.ac.uk/id/eprint/426990
PURE UUID: bfff88e2-a170-4607-b8a0-f709ab119857
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226

Catalogue record

Date deposited: 20 Dec 2018 17:30
Last modified: 20 Jul 2019 01:26

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