A semi-holographic hyperdimensional representation system for hardware-friendly cognitive computing

One of the main, long-term objectives of artificial intelligence is the creation of thinking machines. To that end, substantial effort has been placed into designing cognitive systems; i.e. systems that can manipulate semantic-level information. A substantial part of that effort is oriented towards designing the mathematical machinery underlying cognition in a way that is very efficiently implementable in hardware. In this work, we propose a ‘semi-holographic’ representation system that can be implemented in hardware using only multiplexing and addition operations, thus avoiding the need for expensive multiplication. The resulting architecture can be readily constructed by recycling standard microprocessor elements and is capable of performing two key mathematical operations frequently used in cognition, superposition and binding, within a budget of below 6 pJ for 64-bit operands. Our proposed ‘cognitive processing unit’ is intended as just one (albeit crucial) part of much larger cognitive systems where artificial neural networks of all kinds and associative memories work in concord to give rise to intelligence.

hyperdimensional computing

10.1098/rsta.2019.0162

1364-503X

1-18

Serb, Alexantrou

30f5ec26-f51d-42b3-85fd-0325a27a792c

Kobyzev, Ivan

63a6a10f-8763-41d1-aa6e-a371d8d9047a

Wang, Jiaqi

8b0d7a69-fc27-4344-ab3d-9f05fba98145

Prodromakis, Themis

d58c9c10-9d25-4d22-b155-06c8437acfbf

7 February 2020

Serb, Alexantrou

30f5ec26-f51d-42b3-85fd-0325a27a792c

Kobyzev, Ivan

63a6a10f-8763-41d1-aa6e-a371d8d9047a

Wang, Jiaqi

8b0d7a69-fc27-4344-ab3d-9f05fba98145

Prodromakis, Themis

d58c9c10-9d25-4d22-b155-06c8437acfbf

Serb, Alexantrou, Kobyzev, Ivan, Wang, Jiaqi and Prodromakis, Themis (2020) A semi-holographic hyperdimensional representation system for hardware-friendly cognitive computing. Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences, 378 (2164), 1-18, [20190162]. (doi:10.1098/rsta.2019.0162).

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In preparation date: 11 January 2019

Accepted/In Press date: 5 August 2019

e-pub ahead of print date: 23 December 2019

Published date: 7 February 2020

Additional Information: Funding Information: Data accessibility. This article does not contain any additional data. Authors’ contributions. A.S. conceived the work, defined the basic mathematical machinery and hardware architecture presented in this work and authored the majority of the paper. I.K. contributed to the specification of the mathematical machinery and subsequently refined and solidified it into its final form, checking for functionality and properties. J.W. carried out the optimization, refinement and simulations on the hardware architecture. T.P. aided with the authorship of the paper and provided insight into how this work fits into the bigger picture. Competing interests. We declare we have no competing interests. Funding. This work was supported by the EPSRC (grant no. EP/R024642/1). Acknowledgements. The authors thank Prof. Chris Eliasmith whose work provided much of the inspiration for this work. We also thank Prof. Jesse Hoey for his support and fruitful discussions. Publisher Copyright: © 2019 The Author(s) Published by the Royal Society. All rights reserved. Copyright: Copyright 2020 Elsevier B.V., All rights reserved.

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