On a real-time blind signal separation noise reduction system
On a real-time blind signal separation noise reduction system
Blind signal separation has been studied extensively in order to tackle the cocktail party problem. It explores spatial diversity of the received mixtures of sources by different sensors. By using the kurtosis measure, it is possible to select the source of interest out of a number of separated BSS outputs. Further noise cancellation can be achieved by adding an adaptive noise canceller (ANC) as postprocessing. However, the computation is rather intensive and an online implementation of the overall system is not straightforward. This paper intends to fill the gap by developing an FPGA hardware architecture to implement the system. Subband processing is explored and detailed functional operations are profiled carefully. The final proposed FPGA system is able to handle signals with sample rate over 20000 samples per second.
Yiu, Ka Fai Cedric
f61db65d-2214-48ad-af2d-65a8241a2ce5
Low, Siow Yong
d101f0b9-404e-4e2a-bb4f-a605f0811108
2018
Yiu, Ka Fai Cedric
f61db65d-2214-48ad-af2d-65a8241a2ce5
Low, Siow Yong
d101f0b9-404e-4e2a-bb4f-a605f0811108
Yiu, Ka Fai Cedric and Low, Siow Yong
(2018)
On a real-time blind signal separation noise reduction system.
International Journal of Reconfigurable Computing, 2018, [3721756].
(doi:10.1155/2018/3721756).
Abstract
Blind signal separation has been studied extensively in order to tackle the cocktail party problem. It explores spatial diversity of the received mixtures of sources by different sensors. By using the kurtosis measure, it is possible to select the source of interest out of a number of separated BSS outputs. Further noise cancellation can be achieved by adding an adaptive noise canceller (ANC) as postprocessing. However, the computation is rather intensive and an online implementation of the overall system is not straightforward. This paper intends to fill the gap by developing an FPGA hardware architecture to implement the system. Subband processing is explored and detailed functional operations are profiled carefully. The final proposed FPGA system is able to handle signals with sample rate over 20000 samples per second.
Text
3721756
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Accepted/In Press date: 13 November 2018
e-pub ahead of print date: 4 December 2018
Published date: 2018
Identifiers
Local EPrints ID: 427595
URI: http://eprints.soton.ac.uk/id/eprint/427595
ISSN: 1687-7195
PURE UUID: 3dcff6e7-be97-4c3f-aece-d09520c11624
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Date deposited: 24 Jan 2019 17:30
Last modified: 17 Mar 2024 12:18
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Author:
Ka Fai Cedric Yiu
Author:
Siow Yong Low
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