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Cell flipping with distributed refresh for cache ageing minimization

Cell flipping with distributed refresh for cache ageing minimization
Cell flipping with distributed refresh for cache ageing minimization

CMOS wear-out mechanisms, especially Bias Temperature Instability (BTI), have caused growing concerns about circuit reliability. For cache memories, BTI reduces the static noise margin (SNM), causing unreliable read operations. In practice, error-correction codes (ECCs) are often used to protect data from transient errors in caches, but the limited error correction capabilities are not always enough to overcome BTIinduced read failures. In this paper, we propose a cell flipping technique with distributed refresh phases (CFDR) to minimize cache degradations. The CFDR method flips and refreshes each cache block at different times, minimizing the interruption time and balancing the degradation rate, even for infrequently replaced cache blocks. We evaluate the CFDR technique on an instruction cache in a 32-bit ARM architecture and show our method reduces the number of error bits by 58.86% and 13.59%, compared with an ECC scheme and a traditional cell flipping technique. The cache lifetime can be improved by 125% by using CFDR with less than 1% area overhead, which is not only more effective but also more cost-efficient than the existing techniques.

Bias Temperature Instability, Cell flipping, Error correction code, SRAM cache
98-103
IEEE
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Zwolinski, Mark
adfcb8e7-877f-4bd7-9b55-7553b6cb3ea0

Duan, Shengyu, Halak, Basel and Zwolinski, Mark (2018) Cell flipping with distributed refresh for cache ageing minimization. In Proceedings - 2018 IEEE 27th Asian Test Symposium, ATS 2018. vol. 2018-October, IEEE. pp. 98-103 . (doi:10.1109/ATS.2018.00029).

Record type: Conference or Workshop Item (Paper)

Abstract

CMOS wear-out mechanisms, especially Bias Temperature Instability (BTI), have caused growing concerns about circuit reliability. For cache memories, BTI reduces the static noise margin (SNM), causing unreliable read operations. In practice, error-correction codes (ECCs) are often used to protect data from transient errors in caches, but the limited error correction capabilities are not always enough to overcome BTIinduced read failures. In this paper, we propose a cell flipping technique with distributed refresh phases (CFDR) to minimize cache degradations. The CFDR method flips and refreshes each cache block at different times, minimizing the interruption time and balancing the degradation rate, even for infrequently replaced cache blocks. We evaluate the CFDR technique on an instruction cache in a 32-bit ARM architecture and show our method reduces the number of error bits by 58.86% and 13.59%, compared with an ECC scheme and a traditional cell flipping technique. The cache lifetime can be improved by 125% by using CFDR with less than 1% area overhead, which is not only more effective but also more cost-efficient than the existing techniques.

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More information

Published date: 10 December 2018
Venue - Dates: 27th IEEE Asian Test Symposium, ATS 2018, , Hefei, China, 2018-10-15 - 2018-10-18
Keywords: Bias Temperature Instability, Cell flipping, Error correction code, SRAM cache

Identifiers

Local EPrints ID: 428027
URI: http://eprints.soton.ac.uk/id/eprint/428027
PURE UUID: 08c97d9a-4c88-457e-ad68-863d0351503e
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226
ORCID for Mark Zwolinski: ORCID iD orcid.org/0000-0002-2230-625X

Catalogue record

Date deposited: 07 Feb 2019 17:30
Last modified: 18 Mar 2024 03:19

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Contributors

Author: Shengyu Duan
Author: Basel Halak ORCID iD
Author: Mark Zwolinski ORCID iD

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