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A variation-aware design methodology for distributed arithmetic

A variation-aware design methodology for distributed arithmetic
A variation-aware design methodology for distributed arithmetic

Distributed arithmetic (DA) brings area and power benefits to digital designs relevant to the Internet-of-Things. Therefore, new error resilient techniques for DA computation are urgently required to improve robustness against the process, voltage, and temperature (PVT) variations. This paper proposes a new in-situ timing error prevention technique to mitigate the impact of variations in DA circuits by providing a guardband for significant (most significant bit) computations. This guardband is initially achieved by modifying the sign extension block and carefully gate-sizing. Therefore, least significant bit (LSB) computation can correspond to the critical path, and timing error can be tolerated at the cost of acceptable accuracy loss. Our approach is demonstrated on a 16-tap finite impulse respons (FIR) filter using the 65 nm CMOS process and the simulation results show that this design can still maintain high-accuracy performance without worst case timing margin, and achieve up to 32% power savings by voltage scaling when the worst case margin is considered with only 9% area overhead.

Distributed arithmetic VLSI, Hardware design, PVT variations, Robustness
2079-9292
1-12
Lu, Yue
447d3b21-4bd8-498d-bd22-f018566b4604
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Kazmierski, Tom
a97d7958-40c3-413f-924d-84545216092a
Lu, Yue
447d3b21-4bd8-498d-bd22-f018566b4604
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Kazmierski, Tom
a97d7958-40c3-413f-924d-84545216092a

Lu, Yue, Duan, Shengyu, Halak, Basel and Kazmierski, Tom (2019) A variation-aware design methodology for distributed arithmetic. Electronics, 8 (1), 1-12. (doi:10.3390/electronics8010108).

Record type: Article

Abstract

Distributed arithmetic (DA) brings area and power benefits to digital designs relevant to the Internet-of-Things. Therefore, new error resilient techniques for DA computation are urgently required to improve robustness against the process, voltage, and temperature (PVT) variations. This paper proposes a new in-situ timing error prevention technique to mitigate the impact of variations in DA circuits by providing a guardband for significant (most significant bit) computations. This guardband is initially achieved by modifying the sign extension block and carefully gate-sizing. Therefore, least significant bit (LSB) computation can correspond to the critical path, and timing error can be tolerated at the cost of acceptable accuracy loss. Our approach is demonstrated on a 16-tap finite impulse respons (FIR) filter using the 65 nm CMOS process and the simulation results show that this design can still maintain high-accuracy performance without worst case timing margin, and achieve up to 32% power savings by voltage scaling when the worst case margin is considered with only 9% area overhead.

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electronics-08-00108 - Version of Record
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More information

Accepted/In Press date: 16 January 2019
e-pub ahead of print date: 18 January 2019
Keywords: Distributed arithmetic VLSI, Hardware design, PVT variations, Robustness

Identifiers

Local EPrints ID: 428030
URI: https://eprints.soton.ac.uk/id/eprint/428030
ISSN: 2079-9292
PURE UUID: 7b54ed7c-1348-40d7-acbd-86e2518d9545
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226

Catalogue record

Date deposited: 07 Feb 2019 17:30
Last modified: 14 Mar 2019 01:36

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