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A bit-serial variable-accuracy FFT processor for energy-harvesting systems

A bit-serial variable-accuracy FFT processor for energy-harvesting systems
A bit-serial variable-accuracy FFT processor for energy-harvesting systems

In this paper, a new approach is proposed for designing ultra-low-power FFT (Fast Fourier Transform) system suitable for use in energy harvesting powered sensors. Bit-serial architecture is adopted to reduce the power consumption of butterfly operation. Simulation results show that, compared with state-of-The-Art bit-serial and conventional parallel FFT processors, the proposed technique is superior in terms of silicon area, power consumption, dynamic energy use due to variable precision arithmetic. A sample design of a 64-point FFT shows that the implementation can save about 40% area and 36% leakage power compared with a conventional parallel counterpart, accordingly achieving significant power benefits at a low sample rate and low voltage domain. The dynamic variation of the arithmetic precision can be achieved through a simple modification of the controller with hardware area overhead of 10% gate count.

299-304
IEEE
Lu, Yue
447d3b21-4bd8-498d-bd22-f018566b4604
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a
Liu, Lianxi
3a4aeac7-b7cd-4001-a589-edc234a3bfc7
Lu, Yue
447d3b21-4bd8-498d-bd22-f018566b4604
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a
Liu, Lianxi
3a4aeac7-b7cd-4001-a589-edc234a3bfc7

Lu, Yue, Kazmierski, Tom J. and Liu, Lianxi (2019) A bit-serial variable-accuracy FFT processor for energy-harvesting systems. In 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE. pp. 299-304 . (doi:10.1109/APCCAS.2018.8605629).

Record type: Conference or Workshop Item (Paper)

Abstract

In this paper, a new approach is proposed for designing ultra-low-power FFT (Fast Fourier Transform) system suitable for use in energy harvesting powered sensors. Bit-serial architecture is adopted to reduce the power consumption of butterfly operation. Simulation results show that, compared with state-of-The-Art bit-serial and conventional parallel FFT processors, the proposed technique is superior in terms of silicon area, power consumption, dynamic energy use due to variable precision arithmetic. A sample design of a 64-point FFT shows that the implementation can save about 40% area and 36% leakage power compared with a conventional parallel counterpart, accordingly achieving significant power benefits at a low sample rate and low voltage domain. The dynamic variation of the arithmetic precision can be achieved through a simple modification of the controller with hardware area overhead of 10% gate count.

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More information

Published date: 10 January 2019
Venue - Dates: 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, 2018-10-26 - 2018-10-30

Identifiers

Local EPrints ID: 429138
URI: https://eprints.soton.ac.uk/id/eprint/429138
PURE UUID: 37e62c8d-bb9a-47bd-a2b7-dc2603e4c468

Catalogue record

Date deposited: 22 Mar 2019 17:30
Last modified: 22 Mar 2019 17:30

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