Language and hardware acceleration backend for graph processing

Mokhov, Andrey, De Gennaro, Alessandro, Tarawneh, Ghaith, Wray, Jonny, Lukyanov, Georgy, Mileiko, Sergey, Scott, Joe, Yakovlev, Alex and Brown, Andrew (2019) Language and hardware acceleration backend for graph processing. Grobe, D., Vinco, S. and Patel, H. (eds.) In Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017. vol. 530, Springer. pp. 71-88 . (doi:10.1007/978-3-030-02215-0_4).

Abstract

Graphs are important in many applications. However, their analysis on conventional computer architectures is generally inefficient because it involves highly irregular access to memory when traversing vertices and edges. As an example, when finding a path from a source vertex to a target one the performance is typically limited by the memory bottleneck whereas the actual computation is trivial. This paper presents a methodology for embedding graphs into silicon, where graph vertices become finite state machines communicating via the graph edges. With this approach many common graph analysis tasks can be performed by propagating signals through the physical graph and measuring signal propagation time using the on-chip clock distribution network. This eliminates the memory bottleneck and allows thousands of vertices to be processed in parallel. We present a domain-specific language for graph description and transformation, and demonstrate how it can be used to translate application graphs into an FPGA board, where they can be analyzed up to 1000× faster than on a conventional computer.

This record has no associated files available for download.

Contributors

Download statistics