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Language and hardware acceleration backend for graph processing

Language and hardware acceleration backend for graph processing
Language and hardware acceleration backend for graph processing

Graphs are important in many applications. However, their analysis on conventional computer architectures is generally inefficient because it involves highly irregular access to memory when traversing vertices and edges. As an example, when finding a path from a source vertex to a target one the performance is typically limited by the memory bottleneck whereas the actual computation is trivial. This paper presents a methodology for embedding graphs into silicon, where graph vertices become finite state machines communicating via the graph edges. With this approach many common graph analysis tasks can be performed by propagating signals through the physical graph and measuring signal propagation time using the on-chip clock distribution network. This eliminates the memory bottleneck and allows thousands of vertices to be processed in parallel. We present a domain-specific language for graph description and transformation, and demonstrate how it can be used to translate application graphs into an FPGA board, where they can be analyzed up to 1000× faster than on a conventional computer.

Average shortest path, Breadth-first search, Domain-specific language, Drug discovery, FPGA, Graph processing, Hardware acceleration, Haskell
1876-1100
71-88
Springer Verlag
Mokhov, Andrey
7ad0909b-34e8-4f32-908c-b6406b397776
De Gennaro, Alessandro
8c78f093-4a6b-4e21-90cc-fb90e4a1c8b3
Tarawneh, Ghaith
1b90fbe9-1337-4216-83ba-b01115bf4000
Wray, Jonny
8f1ea9fa-baf5-463b-bd1f-d2c5cc9b0300
Lukyanov, Georgy
3948942d-d0a7-4748-bb1a-d61956e3e73d
Mileiko, Sergey
83a2afc7-8496-45a3-95b7-75a66b2b907c
Scott, Joe
e6edcb6a-2538-4d3a-920b-d64744997c78
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
Brown, Andrew
5c19e523-65ec-499b-9e7c-91522017d7e0
Grobe, D.
Vinco, S.
Patel, H.
Mokhov, Andrey
7ad0909b-34e8-4f32-908c-b6406b397776
De Gennaro, Alessandro
8c78f093-4a6b-4e21-90cc-fb90e4a1c8b3
Tarawneh, Ghaith
1b90fbe9-1337-4216-83ba-b01115bf4000
Wray, Jonny
8f1ea9fa-baf5-463b-bd1f-d2c5cc9b0300
Lukyanov, Georgy
3948942d-d0a7-4748-bb1a-d61956e3e73d
Mileiko, Sergey
83a2afc7-8496-45a3-95b7-75a66b2b907c
Scott, Joe
e6edcb6a-2538-4d3a-920b-d64744997c78
Yakovlev, Alex
d6c94911-c126-4cb7-8f92-d71a898ebbb2
Brown, Andrew
5c19e523-65ec-499b-9e7c-91522017d7e0
Grobe, D.
Vinco, S.
Patel, H.

Mokhov, Andrey, De Gennaro, Alessandro, Tarawneh, Ghaith, Wray, Jonny, Lukyanov, Georgy, Mileiko, Sergey, Scott, Joe, Yakovlev, Alex and Brown, Andrew (2019) Language and hardware acceleration backend for graph processing. Grobe, D., Vinco, S. and Patel, H. (eds.) In Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017. vol. 530, Springer Verlag. pp. 71-88 . (doi:10.1007/978-3-030-02215-0_4).

Record type: Conference or Workshop Item (Paper)

Abstract

Graphs are important in many applications. However, their analysis on conventional computer architectures is generally inefficient because it involves highly irregular access to memory when traversing vertices and edges. As an example, when finding a path from a source vertex to a target one the performance is typically limited by the memory bottleneck whereas the actual computation is trivial. This paper presents a methodology for embedding graphs into silicon, where graph vertices become finite state machines communicating via the graph edges. With this approach many common graph analysis tasks can be performed by propagating signals through the physical graph and measuring signal propagation time using the on-chip clock distribution network. This eliminates the memory bottleneck and allows thousands of vertices to be processed in parallel. We present a domain-specific language for graph description and transformation, and demonstrate how it can be used to translate application graphs into an FPGA board, where they can be analyzed up to 1000× faster than on a conventional computer.

Full text not available from this repository.

More information

e-pub ahead of print date: 20 December 2018
Published date: 2019
Venue - Dates: Forum on specification and Design Languages Conference, FDL 2017, Verona, Italy, 2017-09-18 - 2017-09-20
Keywords: Average shortest path, Breadth-first search, Domain-specific language, Drug discovery, FPGA, Graph processing, Hardware acceleration, Haskell

Identifiers

Local EPrints ID: 429240
URI: https://eprints.soton.ac.uk/id/eprint/429240
ISSN: 1876-1100
PURE UUID: 772e1bb4-a29c-485d-aefa-40e829c1e673

Catalogue record

Date deposited: 22 Mar 2019 17:30
Last modified: 22 Mar 2019 17:30

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