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A cost-efficient error-resilient approach to distributed arithmetic for signal processing

A cost-efficient error-resilient approach to distributed arithmetic for signal processing
A cost-efficient error-resilient approach to distributed arithmetic for signal processing

Distributed arithmetic (DA) brings area and power benefits to digital designs relevant to the Internet-of-Things. Therefore, a new error resilient technique for DA computation is proposed to improve robustness against process, voltage, and temperature variations. The proposed approach mitigates the effect of timing violations by first providing a guardband for significant (most significant bit) computations. This guardband is initially achieved by modifying the order of DA serial operations and borrowing time from the least significant bit (LSB) group. Therefore, LSB computation can correspond to the critical path, and timing error can be tolerated at the cost of acceptable accuracy loss. Moreover, the shifted-phase clock signals are applied on the end-point registers, thereby increasing the global guardband without any effect on system sampling rate. Our approach is demonstrated on a 16-tap FIR filter using the 65 nm CMOS process. The simulation results demonstrate that this design can maintain error-free operation without worst case timing margin, and achieve up to 42% power savings by voltage scaling when the worst case margin is considered. This is at the cost of a 6.3% delay and 7.3% overhead.

Digital signal processing, Distributed arithmetic, Error-resilience, Timing violation
0026-2714
16-21
Lu, Yue
447d3b21-4bd8-498d-bd22-f018566b4604
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a
Lu, Yue
447d3b21-4bd8-498d-bd22-f018566b4604
Duan, Shengyu
cb8534a0-9971-40b9-8c11-72eca641f3a1
Halak, Basel
8221f839-0dfd-4f81-9865-37def5f79f33
Kazmierski, Tom J.
a97d7958-40c3-413f-924d-84545216092a

Lu, Yue, Duan, Shengyu, Halak, Basel and Kazmierski, Tom J. (2019) A cost-efficient error-resilient approach to distributed arithmetic for signal processing. Microelectronics Reliability, 93, 16-21. (doi:10.1016/j.microrel.2018.12.007).

Record type: Article

Abstract

Distributed arithmetic (DA) brings area and power benefits to digital designs relevant to the Internet-of-Things. Therefore, a new error resilient technique for DA computation is proposed to improve robustness against process, voltage, and temperature variations. The proposed approach mitigates the effect of timing violations by first providing a guardband for significant (most significant bit) computations. This guardband is initially achieved by modifying the order of DA serial operations and borrowing time from the least significant bit (LSB) group. Therefore, LSB computation can correspond to the critical path, and timing error can be tolerated at the cost of acceptable accuracy loss. Moreover, the shifted-phase clock signals are applied on the end-point registers, thereby increasing the global guardband without any effect on system sampling rate. Our approach is demonstrated on a 16-tap FIR filter using the 65 nm CMOS process. The simulation results demonstrate that this design can maintain error-free operation without worst case timing margin, and achieve up to 42% power savings by voltage scaling when the worst case margin is considered. This is at the cost of a 6.3% delay and 7.3% overhead.

Full text not available from this repository.

More information

Accepted/In Press date: 16 December 2018
e-pub ahead of print date: 27 December 2018
Published date: 1 February 2019
Keywords: Digital signal processing, Distributed arithmetic, Error-resilience, Timing violation

Identifiers

Local EPrints ID: 429594
URI: https://eprints.soton.ac.uk/id/eprint/429594
ISSN: 0026-2714
PURE UUID: 237ac734-e5d3-4f2a-ba70-1f4391c6e745
ORCID for Basel Halak: ORCID iD orcid.org/0000-0003-3470-7226

Catalogue record

Date deposited: 29 Mar 2019 17:30
Last modified: 20 Jul 2019 00:44

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