Read me file:
University of Southampton – ECS – Ben Fletcher – bjf1g13@ecs.soton.ac.uk

This dataset supports the article entitled: 'A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration', 
accepted for publication in the ACM/IEEE International Symposium on Low Power Electronics and Design , Lausanne, 2019.

Data Supporting Figures:

Fig. 3. Theoretical modelling results: (a) Energy consumption breakdown of the proposed Spike-latency Encoding Transceiver (SET), as N varies, compared to the state-of-the-art (assuming a 12nH inductors with k=0.1), and (b) The variation of total projected energy consumption as channel coupling k and N vary.
Fig. 8. Energy-per-Bit of the NRZ and SET approaches for varying values of N in 65nm CMOS technology.
Fig. 9. Energy breakdown of (a) Existing Non-Return-to-Zero (NRZ) inductive transceiver [5]–[9] and (b) Spike-latency encoding transceiver proposed in this paper
Fig. 10. Energy per bit vs communication distance when using the benchmark NRZ approach [5]–[9], and the proposed spike-latency encoding transceiver.

Data Supporting Tables:

Table 1. Bit Error Rate (BER) comparison of proposed transceiver and existing NRZ transceiver.
Table 2. Area breakdown of existing NRZ and proposed SET transceivers in 65nm CMOS technology.
Table 3. Overall comparison of the poposed SET approach and existing approaches in 65nm technology.

Date of data collection: from Jan 2019 - March 2019
Information about geographic location of data collection: Arm Ltd, Cambridge, UK
Date that the file was created: June 2019