Plane-splitting logic techniques using hybrid CMOS-memristor circuits and systems

Abstract

An important cornerstone of data processing is the ability to efficiently capture structure in data. This entails treating the input space as a hyperplane that needs partitioning. We argue that several modern electronic systems can be understood as carrying out such partitionings: from standard logic gates to Artificial Neural Networks (ANNs) (see Figure 1). More recently, memristive technologies equipped such systems with the benefit of continuous tuneability directly in hardware, thus rendering these reconfigurable in a power and space efficient manner [1], [2]. Here, we demonstrate several proof-of-concept examples where memristors enable circuits optimised to carry out different flavours of the fundamental task of splitting the hyperplane. These include memristor-based computational modules, such as multiple-threshold ‘L-shape’ (Fig. 1f) and receptive field based classifiers (Fig. 1e), that are presented within the context of a unified perspective, the general principle of ‘splitting a hyperplane’ efficiently. & more ...

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Identifiers

ORCID for Georgios Papandroulidakis: orcid.org/0000-0002-9203-2557

ORCID for Themistoklis Prodromakis: orcid.org/0000-0002-6267-6909

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